9202 datasheet(156/175 Pages) STMICROELECTRONICS

156 / 175 page

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

156/175

Figure 78. Input to Output Disable / Enable

Table 120. CPLD Combinatorial Timing (5V Devices)

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount

2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial

output (80-pin package only)

Table 121. CPLD Combinatorial Timing (3V Devices)

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount

2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial

output (80-pin package only)

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Slew

rate(1)

Unit

tPD

(2)

CPLD Input Pin/Feedback to

CPLD Combinatorial Output

+ 2

+ 10

– 2

tEA

CPLD Input to CPLD Output

Enable

+ 10

– 2

tER

CPLD Input to CPLD Output

Disable

+ 10

– 2

tARP

CPLD Register Clear or Preset

Delay

+ 10

– 2

tARPW

CPLD Register Clear or Preset

Pulse Width

+ 10

tARD

CPLD Array Delay

Any

macrocell

+ 2

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Slew

rate(1)

Unit

tPD

(2)

CPLD Input Pin/Feedback to

CPLD Combinatorial Output

+ 4

+ 20

– 6

tEA

CPLD Input to CPLD Output

Enable

+ 20

– 6

tER

CPLD Input to CPLD Output

Disable

+ 20

– 6

tARP

CPLD Register Clear or

Preset Delay

+ 20

– 6

tARPW

CPLD Register Clear or

Preset Pulse Width

+ 20

tARD

CPLD Array Delay

Any

macrocell

+ 4

tER

tEA

INPUT

INPUT TO

OUTPUT

ENABLE/DISABLE

AI02863

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