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ACS8526P датащи(PDF) 49 Page - Semtech Corporation

номер детали ACS8526P
подробное описание детали  Line Card Protection Switch for PDH, SONET or SDH Systems
PDF  74 Pages
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производитель  SEMTECH [Semtech Corporation]
домашняя страница  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

ACS8526P датащи(HTML) 49 Page - Semtech Corporation

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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 4.01/June 2006 © Semtech Corp.
Page 49
www.semtech.com
ACS8526 LC/P LITE
Address (hex):
65
Register Name cnfg_DPLL1_frequency
Description
(R/W) Register to configure
DPLL1 and MUX2 parameters.
Default Value
0000 0001
Bit 7Bit 6
Bit 5Bit 4
Bit 3
Bit 2Bit 1Bit 0
APLL2_for_
DPLL1_E1/DS1
DPLL1_freq_to_APLL2
DPLL1_frequency
Bit No.
Description
Bit Value
Value Description
7Not used.
-
-
6
APLL2_for_DPLL1_E1/DS1
Register bit to control MUX2 which selects whether
the APLL2 takes its input from DPLL2 or DPLL1. If
DPLL1 is selected then the frequency is controlled
by Bits [5:4], DPLL1_freq_to_APLL2.
0
1
APLL2 takes its input from DPLL2.
APLL2 takes its input from DPLL1.
[5:4]
DPLL1_freq_to_APLL2
Register to select the frequency/mode of DPLL1
which is driven to the APLL2 when selected by Bit 6,
APLL2_for_DPLL1_E1/DS1.
00
01
10
11
12E1, APLL2 frequency = 98.304 MHz.
16E1, APLL2 frequency = 131.072 MHz.
24DS1, APLL2 frequency = 148.224 MHz.
16DS1, APLL2 frequency = 98.816 MHz.
3Not used.
-
-
[2:0]
DPLL1_frequency
Register to configure the frequency of operation of
DPLL1/APLL1. This register affects the frequencies
available at outputs O1 and O2, see Reg. 61 and
Reg. 62.
000
001
010
011
100
101
110
111
77.76 MHz, digital feedback,
APLL1 frequency = 311.04 MHz.
77.76 MHz, analog feedback, (via APLL3)
APLL1 frequency = 311.04 MHz.
12E1, APLL1 frequency = 98.304 MHz.
16E1, APLL1 frequency = 131.072 MHz.
24DS1, APLL1 frequency = 148.224 MHz.
16DS1, APLL1 frequency = 98.816 MHz.
Not used.
Not used.
Note...001 is the only selection that does not
bypass APLL3. All other selections use digital
feedback.
Address (hex):
66
Register Name cnfg_DPLL2_bw
Description
(R/W) Register to configure the
bandwidth of DPLL2.
Default Value
0000 0000
Bit 7Bit 6
Bit 5Bit 4
Bit 3
Bit 2Bit 1Bit 0
DPLL2_bandwidth
Bit No.
Description
Bit Value
Value Description
[7:2]
Not used.
-
-



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