ACS8526P datasheet(39/74 Pages) SEMTECH

39 / 74 page

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 4.01/June 2006 © Semtech Corp.

Page 39

www.semtech.com

ACS8526 LC/P LITE

Address (hex):

Description

(R/W) Configures the electrical

compatibility of the differential

output driver to be 3 V PECL or

3V LVDS.

Default Value

1100 0010

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

Output O1_LVDS_PECL

Bit No.

Description

Bit Value

Value Description

[7:2]

Not used.

[1:0]

Output O1_LVDS_PECL

Selection of the electrical compatibility of Output O1

between 3 V PECL and 3 V LVDS.

Output O1 disabled.

Output O1 3 V PECL compatible.

Output O1 3 V LVDS compatible.

Not used.

Address (hex):

Description

(R/W) Register to select

automatic bandwidth selection for

DPLL1 path

Default Value

1001 1000

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

auto_BW_sel

DPLL1_lim_int

Bit No.

Description

Bit Value

Value Description

auto_BW_sel

Bit to select locked bandwidth (Reg. 67) or

acquisition bandwidth (Reg. 69) for DPLL1.

Automatically selects either locked or acquisition

bandwidth as appropriate.

Always selects locked bandwidth.

[6:4]

Not used.

DPLL1_lim_int

When set to 1 the integral path value of DPLL1 is

limited or frozen when DPLL1 reaches either min. or

max. frequency. This can be used to minimize

subsequent overshoot when the DPLL is pulling in.

Note that when this bit is enabled, the reported

frequency value, via current_DPLL_freq (Reg. 0C,

0D and 07), is also frozen.

DPLL value frozen.

DPLL not frozen.

[2:0]

Not used.

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