ATAR092 datasheet(6/107 Pages) ATMEL

6 / 107 page

4535E–4BMCU–05/07

ATAR092/ATAR892

Figure 4-4.

Programming Model

4.2.3.2

RAM Address Registers

The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These

registers allow access to any of the 256 RAM nibbles.

4.2.3.3

Expression Stack Pointer (SP)

The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expression

stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or

post-decremented if a nibble is removed from the stack. Every post-decrement operation moves

the item (TOS-1) to the TOS register before the SP is decremented. After a reset the stack

pointer has to be initialized with >SP S0 to allocate the start address of the expression stack

area.

4.2.3.4

Return Stack Pointer (RP)

The return stack pointer points to the top element of the 12-bit wide return stack. The pointer

automatically pre-increments if an element is moved onto the stack, or it post-decrements if an

element is removed from the stack. The return stack pointer increments and decrements in

steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left

unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset

the return stack pointer has to be initialized via >RP FCh.

4.2.3.5

RAM Address Registers (X and Y)

The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves

the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM

location. By using either the pre-increment or post-decrement addressing mode arrays in the

RAM can be compared, filled or moved.

TOS

CCR

-- B

Program Counter

Return Stack Pointer

Expression Stack Pointer

RAM Address Register (Y)

RAM Address Register (X)

Top of Stack Register

Condition Code Register

Interrupt Enable

Branch

Reserved

Carry/Borrow

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