ATAR092 datasheet(21/107 Pages) ATMEL

21 / 107 page

4535E–4BMCU–05/07

ATAR092/ATAR892

Peripheral Modules

5.1

Addressing Peripherals

Accessing the peripheral modules takes place via the I/O bus (see Figure 5-1). The IN or OUT

instructions allow direct addressing of up to 16 I/O modules. A dual register addressing scheme

has been adopted to enable direct addressing of the primary register. To address the auxiliary

OUT) to the module address will read (or write into) the module primary register. Accessing the

auxiliary register is performed with the same instruction preceded by writing the module address

into the auxiliary switching module. Byte wide registers are accessed by multiple IN- (or OUT-)

instructions. For more complex peripheral modules, with a larger number of registers, extended

addressing is used. In this case a bank of up to 16 subport registers are indirectly addressed

with the subport address. The first OUT-instruction writes the subport address to the sub

address register, the second IN- or OUT-instruction reads data from or writes data to the

addressed subport.

Figure 5-1.

Example of I/O Addressing

Auxiliary Switch

Primary Reg.

Module

Subport 0

Subport 1

Subaddress Reg.

(Address Pointer)

Subport EH

Bank of

Primary Regs.

Subport FH

Primary Reg.

Auxiliary Reg.

I/O bus

To Other Modules

Module ASW

Module M1

Module M2

Module M3

Indirect Subport Access

(Subport Register Write)

(Subport Register Write Byte)

(Subport Register Read)

1) Addr. (SPort) Addr. (M1) OUT

Example of

qFORTH

Program

Code

Addr. (ASW) = Auxiliary Switch Module Address

Addr. (Mx) = Module Mx Address

Addr. (SPort) = Subport Address

Aux._Data (lo) = Data to Be Written into Auxiliary Register

(low nibble)

Aux._Data = Data to be written into Auxiliary Register

Prim._Data = Data to be written into Primary Register

Aux._Data (hi) = Data to be written into Auxiliary Register (high nibble)

SPort_Data(lo) = Data to be written into Subport (low nibble)

SPort_Data(hi) = Data to be written into Subport (high nibble)

(lo) = SPort_Data (low nibble)

(hi) = SPort_Data (high nibble)

Dual Register Access

(Primary Register Write)

(Auxiliary Register Write)

5) Aux._Data Addr. (M2) OUT

4) Addr. (M2) Addr. (ASW) OUT

3) Prim._Data Addr. (M2) OUT

Single Register Access

(Primary Register Write)

6) Prim._Data Addr. (M3) OUT

(Primary Register Read)

Addr. (M3) IN

(Primary Register Read)

Addr. (M2) IN

(Auxiliary Register Read)

4) Addr. (M2) Addr. (ASW) OUT

(Auxiliary Register Write Byte)

4) Addr. (M2) Addr. (ASW) OUT

5) Aux._Data (hi) Addr. (M2) OUT

5) Aux._Data (lo) Addr. (M2) OUT

Addr. (M2) IN

2) SPort_Data Addr. (M1) OUT

1) Addr. (SPort) Addr. (M1) OUT

2) SPort_Data (lo) Addr. (M1) OUT

2) SPort_Data (hi) Addr. (M1) OUT

1) Addr. (SPort) Addr. (M1) OUT

Addr. (M1) IN

(Subport Register Read Byte)

1) Addr. (SPort) Addr. (M1) OUT

Addr. (M1) IN (lo)

Addr. (M1) IN (hi)

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