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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT89C5131A-RDTUL датащи(PDF) 17 Page - ATMEL Corporation |
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AT89C5131A-RDTUL датащи(HTML) 17 Page - ATMEL Corporation |
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17 / 186 page  17 AT89C5131A-L 4338F–USB–08/07 Table 15. CKCON1 (S:AFh) Clock Control Register 1 Reset Value = 0000 0000b Table 16. PLLCON (S:A3h) PLL Control Register Reset Value = 0000 0000b Table 17. PLLDIV (S:A4h) PLL Divider Register Reset Value = 0000 0000 7 6 5 4 3 2 1 0 - - - - - - - SPIX2 Bit Number Bit Mnemonic Description 7-1 - Reserved The value read from this bit is always 0. Do not set this bit. 0 SPIX2 SPI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 7 6 5 4 3 2 1 0 - - - - - EXT48 PLLEN PLOCK Bit Number Bit Mnemonic Description 7-3 - Reserved The value read from this bit is always 0. Do not set this bit. 2 EXT48 External 48 MHz Enable Bit Set this bit to bypass the PLL and disable the crystal oscillator. Clear this bit to select the PLL output as USB clock and to enable the crystal oscillator. 1 PLLEN PLL Enable Bit Set to enable the PLL. Clear to disable the PLL. 0 PLOCK PLL Lock Indicator Set by hardware when PLL is locked. Clear by hardware when PLL is unlocked. 7 6 5 4 3 2 1 0 R3 R2 R1 R0 N3 N2 N1 N0 Bit Number Bit Mnemonic Description 7-4 R3:0 PLL R Divider Bits 3-0 N3:0 PLL N Divider Bits |
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