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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT89C5131A-RDTUL датащи(PDF) 13 Page - ATMEL Corporation |
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AT89C5131A-RDTUL датащи(HTML) 13 Page - ATMEL Corporation |
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13 / 186 page  13 AT89C5131A-L 4338F–USB–08/07 Clock Controller Introduction The AT89C5131A-L clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are gen- erated by this controller. The AT89C5131A-L X1 and X2 pins are the input and the output of a single-stage on- chip inverter (see Figure 7) that can be configured with off-chip components as a Pierce oscillator (see Figure 8). Value of capacitors and crystal characteristics are detailed in the section “DC Characteristics”. The X1 pin can also be used as input for an external 48 MHz clock. The clock controller outputs three different clocks as shown in Figure 7: • a clock for the CPU core • a clock for the peripherals which is used to generate the Timers, PCA, WD, and Port sampling clocks • a clock for the USB controller These clocks are enabled or disabled depending on the power reduction mode as detailed in Section “Power Management”, page 152. Figure 7. Oscillator Block Diagram Oscillator Two clock sources are available for CPU: • Crystal oscillator on X1 and X2 pins: Up to 32 MHz • External 48 MHz clock on X1 pin In order to optimize the power consumption, the oscillator inverter is inactive when the PLL output is not selected for the USB device. X1 X2 PD PCON.1 IDL PCON.0 Peripheral CPU Core 0 1 X2 CKCON.0 ÷ 2 Clock Clock EXT48 PLLCON.2 0 1 PLL USB Clock |
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