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AT89C5130A-RDTUM датащи(PDF) 60 Page - ATMEL Corporation |
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AT89C5130A-RDTUM датащи(HTML) 60 Page - ATMEL Corporation |
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60 / 188 page ![]() 60 4337K–USB–04/08 AT89C5130A/31A-M Reset Value = 00XX X000b Not bit addressable The CMOD register includes three additional bits associated with the PCA (See Figure 14-1 and Table 14-1). • The CIDL bit allows the PCA to stop during idle mode. • The WDTE bit enables or disables the watchdog function on module 4. • The ECF bit when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (see Table 14-2). • Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. • Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. • Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags can only be cleared by software. Table 14-2. CCON Register CCON - PCA Counter Control Register (D8h) 7 6 5 4 3 2 1 0 CF CR – CCF4 CCF3 CCF2 CCF1 CCF0 Bit Number Bit Mnemonic Description 7 CF PCA Counter Overflow flag Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. 6 CR PCA Counter Run control bit Must be cleared by software to turn the PCA counter off. Set by software to turn the PCA counter on. 5 – Reserved The value read from this bit is indeterminate. Do not set this bit. 4 CCF4 PCA Module 4 interrupt flag Must be cleared by software. Set by hardware when a match or capture occurs. 3 CCF3 PCA Module 3 interrupt flag Must be cleared by software. Set by hardware when a match or capture occurs. 2 CCF2 PCA Module 2 interrupt flag Must be cleared by software. Set by hardware when a match or capture occurs. |
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