ACEX1K datasheet(39/86 Pages) ALTERA

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Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Notes to tables:

(1)

To implement the ClockLock and ClockBoost circuitry with the Altera software, designers must specify the input

frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The

fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency during device

operation. Simulation does not reflect this parameter.

(2)

Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.

(3)

During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If

the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during

configuration because the tLOCK value is less than the time required for configuration.

(4)

The tJITTER specification is measured under long-term observation. The maximum value for tJITTER is 200 ps if

tINCLKSTB is lower than 50 ps.

I/O

Configuration

This section discusses the PCI pull-up clamping diode option, slew-rate

control, open-drain output option, and MultiVolt I/O interface for

ACEX 1K devices. The PCI pull-up clamping diode, slew-rate control, and

open-drain output options are controlled pin-by-pin via Altera software

logic options. The MultiVolt I/O interface is controlled by connecting

VCCIO to a different voltage than VCCINT. Its effect can be simulated in the

Altera software via the Global Project Device Options dialog box (Assign

menu).

Table 12. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Input rise time

5ns

Input fall time

5ns

tINDUTY

Input duty cycle

fCLK1

Input clock frequency (ClockBoost clock

multiplication factor equals 1)

MHz

fCLK2

Input clock frequency (ClockBoost clock

multiplication factor equals 2)

MHz

fCLKDEV

Input deviation from user specification in

the software (1)

25,000

PPM

tINCLKSTB Input clock stability (measured between

adjacent clocks)

100

tLOCK

Time required for ClockLock or ClockBoost

to acquire lock (3)

µs

tJITTER

Jitter on ClockLock or ClockBoost-

generated clock (4)

tINCLKSTB < 100

250 (4)

tINCLKSTB < 50

200 (4)

tOUTDUTY Duty cycle for ClockLock or ClockBoost-

generated clock

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