TSS463B datasheet(39/59 Pages) ATMEL

39 / 59 page

TSS463B

4102E–AUTO–12/04

Message Length And Status

The message length and status register at address (base_address + 0x03) is also 8 bits

wide. It indicates the length of reserved for the message in the Message DATA RAM

area.

•

Read/Write register.

M_L [4:0]: Message Length

The 5 high bits of this register allows the user to specify either the length of the message

to be transmitted, or the maximum length of a message receivable in the pointed recep-

tion buffer.

Note: The first byte in this register does not contain data, but the length of the message

received. This implies that the length value has to be equal to or greater than the maxi-

mum length of a message to be received in this buffer (or the length of a message to be

transmitted) plus 1, thus allowing a maximum length of 30 bytes and a minimum length

of 0 byte.

If the value of this field is “illegal” (i.e 0x00) then this message pointer is defined as

being a link (see Message pointer and register and “Linked Channels” on page 52).

CHER: Channel Error Status

and Abort Command

As status, this bit is set by the TSS463B when error occurs in transmission or on a

received frame. The user must reset it.

To abort the transmission defined in the channel, this bit can be set to 1 by the user (see

Section “Activate, Idle and Sleep Modes”, page 51 and “Abort” on page 49)

CHTx: Channel Transmitted and

Transmit Enable Command

CHRx: Channel Received and

Receive Enable Command

The 2 low order bits of this register contain the message status. Together with the RNW

and RTR bits of the command register (base_address + 0x01), they define the message

type of this channel (see section “Message Types” on page 44). As a general rule, the

status bits are only set by the TSS463B, so the user must reset them to perform a trans-

mission (CHTx) or/and a reception (CHRx). The received and transmitted bits are only

set if the corresponding frame is without errors or if the retry count has been exceeded.

765

210

M_L 4

M_L 3

M_L 2

M_L 1

M_L 0

CHER

CHTx

CHRx

base_address

+ 0x03

M_L [4:0] = 0x00

Linked channel

M_L [4:0] = 0x01

Frame with no DATA field

(1)

M_L [4:0] = 0x02

Frame with 1 DATA byte

- - - - - - -

- - - - - - - - - - - - - - - - - - - - - -

M_L [4:0] = 0x1D

Frame with 28 DATA bytes

M_L [4:0] = 0x1E

Frame with 29 DATA bytes

M_L [4:0] = 0x1F

Frame with 30 DATA bytes

Note:

Different of a reply request frame with no in-frame reply (deferred reply).

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