USBUFxxW6

5/9

ESD Surge

Vinput

Voutput

Rload

Rg

Rt

S1

Rd

V

BR

V

BR

V

PP

Device

to be

protected

USBUF01W6

Rd

S2

Fig. A5: USBUFxxW6 ESD clamping behavior

TEST BOARD

ESD

SURGE

16kV

Air

Discharge

Vin

Vout

Fig. A6: Measurement board

To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical

dynamical resistance value Rd. By taking into account these following hypothesis : Rt>Rd, Rg>Rd and

Rload>Rd, it gives these formulas:

Vinput

RV

RV

R

gBR

d

g

g

=

+

..

Voutput

R V

R Vinput

R

tBR

d

t

=

+

..

The results of the calculation done for Vg=8kV, Rg=330

and Rd = 1

Ω (typ.) give:

Vinput = 31.2 V

Voutput = 7.95 V

This confirms the very low remaining voltage across the device to be protected. It is also important to note

that in this approximation the parasitic inductance effect was not taken into account. This could be few

tenths of volts during few ns at the Vinput side. This parasitic effect is not present at the Voutput side due

the low current involved after the resistance Rt.

The measurements done hereafter show very clearly (Fig. A7) the high efficiency of the ESD protection :

- no influence of the parasitic inductances on Voutput stage