5

7593GS–AVR–03/08

AT90USB64/128

AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1.

Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

PROGRAM

COUNTER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

REGISTER

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTE

DATA DIR.

REG. PORTA

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTE

DATA REGISTER

PORTA

DATA REGISTER

PORTD

INTERRUPT

UNIT

EEPROM

SPI

USART0

STATUS

REGISTER

Z

Y

X

ALU

PORTB DRIVERS

PORTE DRIVERS

PORTA DRIVERS

PORTF DRIVERS

PORTD DRIVERS

PORTC DRIVERS

PB7 - PB0

PE7 - PE0

PA7 - PA0

PF7 - PF0

VCC

AGND

GND

AREF

CONTROL

LINES

PC7 - PC0

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

8-BIT DATA BUS

AVCC

USB

TIMING AND

CONTROL

OSCILLATOR

CALIB. OSC

DATA DIR.

REG. PORTC

DATA REGISTER

PORTC

ON-CHIP DEBUG

JTAG TAP

PROGRAMMING

LOGIC

BOUNDARY-

SCAN

DATA DIR.

REG. PORTF

DATA REGISTER

PORTF

ADC

POR - BOD

RESET

PD7 - PD0

TWO-WIRE SERIAL

INTERFACE

PLL