8

7593GS–AVR–03/08

AT90USB64/128

2.2.9

D-

USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D-

connector pin with a serial 22 Ohms resistor.

2.2.10

D+

USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+

connector pin with a serial 22 Ohms resistor.

2.2.11

UGND

USB Pads Ground.

2.2.12

UVCC

USB Pads Internal Regulator Input supply voltage.

2.2.13

UCAP

USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-

itor (1µF).

2.2.14

VBUS

USB VBUS monitor and OTG negociations.

2.2.15

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page

58. Shorter pulses are not guaranteed to generate a reset.

2.2.16

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.2.17

XTAL2

Output from the inverting Oscillator amplifier.

2.2.18

AVCC

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-

through a low-pass filter.

2.2.19

AREF

This is the analog reference pin for the A/D Converter.

3.

About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

These code examples assume that the part specific header file is included before compilation.

For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"