CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

DS875F1

Copyright 2008 Cirrus Logic

9

CONFIDENTIAL

4.2.6 Hardware Watchdog Timer

The CS48DV2B has an integrated watchdog timer that acts as a “health” monitor for the DSP. The

watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This

peripheral ensures that the CS48DV2B will reset itself in the event of a temporary system failure. In

stand-alone mode (that is, no host MCU), the DSP will reboot from external FLASH. In slave mode

(that is, host MCU present) a GPIO will be used to signal the host that the watchdog has expired and

the DSP should be rebooted and re-configured.

4.3 DSP I/O Description

4.3.1 Multiplexed Pins

Many of the CS48DV2B pins are multi-functional. For details on pin functionality please refer to the

CS485xx Hardware User’s Manual.

4.3.2 Termination Requirements

Open-drain pins on the CS48DV2B must be pulled high for proper operation. Please refer to the

CS485xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up

resistor is required for proper operation.

Mode select pins in the CS48DV2B are used to select the boot mode upon the rising edge from

reset. A detailed explanation of termination requirements for each communication mode select pin

can be found in the CS485xx Hardware User’s Manual.

4.3.3 Pads

The CS48DV2B I/Os operate from the 3.3 V supply and are 5 V tolerant.

4.4 Application Code Security

The external program code may be encrypted by the programmer to protect any intellectual property

it may contain. A secret, customer-specific key is used to encrypt the program code that is to be

stored external to the device. Please contact your local Cirrus representative for details.