CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

8

Copyright 2008 Cirrus Logic

DS875F1

CONFIDENTIAL

modes are supported, with flexible start address and increment controls. The service intervals for

each DMA channel, as well as up to 6 interrupt events, are programmable.

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz.

The port is capable of accepting PCM or DSD formats. Up to 32-bit word lengths are supported. DSD

is supported and internally converted to PCM before processing. The DAI also supports a time

division multiplexed (TDM) one-line data mode that packs multiple channels of PCM audio input on a

single data line. The total number of channels that are possible depends on the ratio of SCLK to

LRCLK.

The port has two independent slave-only clock domains. Each data input can be independently

assigned to a clock domain. The sample rate of the input clock domains can be determined

automatically by the DSP, off-loading the task of monitoring the SPDIF receiver from the host. A time-

stamping feature allows the input data to be sample-rate converted via software.

4.2.2 Digital Audio Output Port (DAO)

DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as

192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a

clock slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can

be re-configured as a SPDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with

embedded clock on a single line).

The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple

channels of PCM audio on a single data line.

modes. Master/Slave operation is chosen by mode select pins when the CS48DV2B comes out of

Reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed

must always be

the communications interface (SCP_BSY) and a pin to indicate when the DSP has a message for the

host (SCP_IRQ).

4.2.4 GPIO

Many of the CS48DV2B peripheral pins are multiplexed with GPIO. Each GPIO can be configured as

an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising

edge, falling edge, active-low, or active-high.

4.2.5 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used

to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock

domain can be output on the DAO port for driving audio converters. The CS48DV2B defaults to

running from the external reference frequency and is switched to use the PLL output after overlays

have been loaded and configured, either through master boot from an external FLASH or through

host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output

frequency ratio is selectable between 1:1 (default) or 2:1.