PCF8562TTSLASH2 datasheet(17/36 Pages) NXP

17 / 36 page

PCF8562_3

Product data sheet

Rev. 3 — 2 December 2008

17 of 36

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

7.12 Output bank selector

The output bank selector selects one of the four bits per display RAM address for transfer

to the display latch. The actual bit chosen depends on the selected LCD drive mode in

operation and on the instant in the multiplex sequence.

• In 1:4 mode, all RAM addresses of bit 0 are selected, these are followed by the

contents of bit 1, bit 2 and then bit 3.

• In 1:3 mode, bits 0, 1 and 2 are selected sequentially

• In 1:2 mode, bits 0 and 1 are selected

• In static mode, bit 0 is selected

The SYNC signal resets these sequences to the following starting points:

• Bit 3 for 1:4 mode

• Bit 2 for 1:3 mode

• Bit 1 for 1:2 mode

• Bit 0 for static mode

The PCF8562 includes a RAM bank switching feature in the static and 1:2 drive modes. In

the static drive mode, the bank-select command (see Section 7.17) may request the

contents of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 mode, the

contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision

for preparing display information in an alternative bank and to be able to switch to it once it

is assembled.

7.13 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive conﬁguration.

The bank-select command (see Section 7.17) can be used to load display data in bit 2 in

static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector functions are

independent of the output bank selector.

7.14 Subaddress counter

The storage of display data is determined by the contents of the subaddress counter.

Storage is allowed to take place only when the contents of the subaddress counter agree

with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is

deﬁned by the device-select command (see Section 7.17). If the contents of the

subaddress counter and the hardware subaddress do not agree then data storage is

inhibited but the data pointer is incremented as if data storage had taken place. The

subaddress counter is also incremented when the data pointer overﬂows.

The hardware subaddress must not be changed while the device is being accessed on the

I2C-bus interface.

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