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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC2220 датащи(PDF) 39 Page - NXP Semiconductors |
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LPC2220 датащи(HTML) 39 Page - NXP Semiconductors |
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39 / 50 page  LPC2210_2220_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 11 December 2008 39 of 50 NXP Semiconductors LPC2210/2220 16/32-bit ARM microcontrollers [1] Except on initial access, in which case the address is set up Tcy(CCLK) earlier. [2] Tcy(CCLK) = 1⁄CCLK. [3] Latest of address valid, CS LOW, OE LOW to data valid. [4] See the LPC2210/20 user manual UM10114_1 for a description of the WSTn bits. [5] Address valid to data valid. [6] Earliest of CS HIGH, OE HIGH, address change to data invalid. tBLSHDNV BLS HIGH to data invalid time [2] (2 × T cy(CCLK)) − 5 - (2 × T cy(CCLK))+5 ns tCHDV XCLK HIGH to data valid time - - 10 ns tCHWEL XCLK HIGH to WE LOW time - - 10 ns tCHBLSL XCLK HIGH to BLS LOW time - - 10 ns tCHWEH XCLK HIGH to WE HIGH time - - 10 ns tCHBLSH XCLK HIGH to BLS HIGH time - - 10 ns tCHDNV XCLK HIGH to data invalid time - - 10 ns Table 14. External memory interface dynamic characteristics …continued CL = 25 pF; Tamb =40 °C. Symbol Parameter Conditions Min Typ Max Unit Table 15. Standard read access specifications Access cycle Max frequency WST setting WST ≥ 0; round up to integer Memory access time requirement standard read standard write burst read - initial burst read - subsequent 3 × N/A f MAX 2 WST 1 + t RAM 20 ns + -------------------------------- ≤ WST 1 t RAM 20 ns + t cy CCLK () -------------------------------- ≥ 2 – t RAM t cy CCLK () 2 WST 1 + () × 20 ns – ≤ f MAX 1WST 2 + t WRITE 5ns + ---------------------------------- ≤ WST 2 t WRITE t CYC 5 + – t cy CCLK () -------------------------------------------- ≥ t WRITE t cy CCLK () 1 WST 2 + () × 5ns – ≤ f MAX 2 WST 1 + t INIT 20 ns + -------------------------------- ≤ WST 1 t INIT 20 ns + t cy CCLK () -------------------------------- ≥ 2 – t INIT t cy CCLK () 2 WST 1 + () × 20 ns – ≤ f MAX 1 t ROM 20 ns + --------------------------------- ≤ t ROM t cy CCLK () 20 ns – ≤ |
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