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LPC2220 датащи(PDF) 38 Page - NXP Semiconductors

номер детали LPC2220
подробное описание детали  16/32-bit ARM microcontrollers; flashless, with 10-bit ADC and external memory interface
PDF  50 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC2220 датащи(HTML) 38 Page - NXP Semiconductors

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LPC2210_2220_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
38 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
Table 14.
External memory interface dynamic characteristics
CL = 25 pF; Tamb =40 °C.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Common to read and write cycles
tCHAV
XCLK HIGH to address valid
time
-
-
10
ns
tCHCSL
XCLK HIGH to CS LOW time
-
-
10
ns
tCHCSH
XCLK HIGH to CS HIGH
time
-
-
10
ns
tCHANV
XCLK HIGH to address
invalid time
-
-
10
ns
Read cycle parameters
tCSLAV
CS LOW to address valid
time
[1]
−5
-
+10
ns
tOELAV
OE LOW to address valid
time
[1]
−5
-
+10
ns
tCSLOEL
CS LOW to OE LOW time
−5
-
+5
ns
tam
memory access time
[2][3]
[4]
(Tcy(CCLK) × (2 + WST1)) +
(
−20)
--
ns
tam(ibr)
memory access time (initial
burst-ROM)
[2][3]
[4]
(Tcy(CCLK) × (2 + WST1)) +
(
−20)
--
ns
tam(sbr)
memory access time
(subsequent burst-ROM)
[2][5] Tcy(CCLK) +(−20)
-
-
ns
th(D)
data hold time
[6] 0-
-
ns
tCSHOEH
CS HIGH to OE HIGH time
−5
-
+5
ns
tOEHANV
OE HIGH to address invalid
time
−5
-
+5
ns
tCHOEL
XCLK HIGH to OE LOW time
−5
-
+5
ns
tCHOEH
XCLK HIGH to OE HIGH
time
−5
-
+5
ns
Write cycle parameters
tAVCSL
address valid to CS LOW
time
[1] Tcy(CCLK) − 10
-
-
ns
tCSLDV
CS LOW to data valid time
−5
-
+5
ns
tCSLWEL
CS LOW to WE LOW time
−5
-
+5
ns
tCSLBLSL
CS LOW to BLS LOW time
−5
-
+5
ns
tWELDV
WE LOW to data valid time
−5
-
+5
ns
tCSLDV
CS LOW to data valid time
−5
-
+5
ns
tWELWEH
WE LOW to WE HIGH time
[2][4] Tcy(CCLK) × (1 + WST2) − 5-
Tcy(CCLK) ×
(1 + WST2) + 5
ns
tBLSLBLSH
BLS LOW to BLS HIGH time
[2][4] Tcy(CCLK) × (1 + WST2) − 5-
Tcy(CCLK) ×
(1 + WST2) + 5
ns
tWEHANV
WE HIGH to address invalid
time
[2] Tcy(CCLK) − 5-
Tcy(CCLK) +5
ns
tWEHDNV
WE HIGH to data invalid time
[2] (2
× T
cy(CCLK)) − 5
-
(2
× T
cy(CCLK))+5
ns
tBLSHANV
BLS HIGH to address invalid
time
[2] Tcy(CCLK) − 5-
Tcy(CCLK) +5
ns



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