PCM1691 datasheet(21/47 Pages) TI

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SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM

Stateof

Synchronization

Synchronous

Normal

Synchronous

Asynchronous

DAC

VOUTx

VCOM

(0.5VCC1)

Within1/f

38/f (single,dualrate)

29/f (quadrate)

UndefinedData

ZERO FLAG

PCM1691

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The PCM1691 operates under the system clock (SCKI) and the audio sampling rate (LRCK). Therefore, SCKI

and LRCK must have a specific relationship. The PCM1691 does not need a specific phase relationship between

the audio interface clocks (LRCK, BCK) and the system clock (SCKI), but does require a specific frequency

relationship (ratiometric) between LRCK, BCK, and SCKI.

If the relationship between SCKI and LRCK changes more than ±2 BCK clocks because of jitter, sampling

frequency change, etc., the DAC internal operation stops within 1/fS, and the analog output is forced into VCOM

(0.5 VCC1) until re-synchronization among SCKI, LRCK, and BCK completes, and then either 38/fS (single, dual

rate) or 29/fS (quad rate) passes. In the event the change is less than ±2 BCKs, re-synchronization does not

occur, and this analog output control and discontinuity does not occur.

Figure 31 shows the DAC analog output during loss of synchronization. During undefined data periods, some

noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined (or

zero) data to normal data creates a discontinuity of data on the analog outputs, which may then generate some

noise in the audio signal.

The DAC outputs (VOUTx) hold the previous state if the system clock halts, but the asynchronous and

re-synchronization processes will occur after the system clock resumes.

Figure 31. DAC Outputs During Loss of Synchronization

The PCM1691 has two ZERO flag pins (ZERO1 and ZERO2) that can be assigned to the combinations shown in

Table 8. Zero flag combinations are selected through the AZRO[1:0] bits in control register 70 (46h). If the input

data of all the assigned channels remain at '0' for 1024 sampling periods (LRCK clock periods), the ZERO1/2 bits

are set to a high level, logic '1' state. Furthermore, if the input data of any of the assigned channels read '1', the

ZERO1/2 are set to a low level, logic '0' state, immediately. Zero data detection is supported for 16-/20-/24-bit

data width, but is not supported for 32-bit data width.

The active polarity of the zero flag output can be inverted through the ZREV bit in control register 70 (46h). The

reset default is active high for zero detection.

In parallel hardware control mode, ZERO1 and ZERO2 are fixed with combination A, shown in Table 8.

Table 8. Zero Flag Outputs Combination

ZERO FLAG COMBINATION

ZERO1

ZERO2

DIN1, left channel

DIN1, right channel

DIN1–4

DIN4

DIN1–3

DIN1

DIN2–4

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