PCM1691 datasheet(16/47 Pages) TI

16 / 47 page

RESET OPERATION

VDD

0.5

VCC

(VDD=3.3V,typ)

VCOM

(0.5

VCC1)

3846

SCKI

NormalOperation

SynchronousClocks

(VDD=2.2V,typ)

RST

InternalReset

VOUT1-8

SCKI,

BCK,

LRCK

VDD

SynchronousClocks

Power-Down

NormalOperation

SynchronousClocks

SCKI,

BCK,

LRCK

RST

InternalReset

VOUT1-8

0.5

VCC

(VDD=3.3V,typ)

3846

SCKI

100ns(min)

PCM1691

SBAS450 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com

The PCM1691 has both an internal power-on reset circuit and an external reset circuit. The sequences for both

reset circuits are shown in Figure 20 and Figure 21. Figure 20 illustrates the timing at the internal power-on reset.

Initialization is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset is

released after 3846 SCKI clock cycles from power-on, if RST is held high and SCKI is provided. VOUTx from the

DAC is forced to the VCOM level initially (that is, 0.5 × VCC1) and settles at a specified level according to the

rising VCC. If synchronization among SCKI, BCK, and LRCK is maintained, VOUTx provides an output that

corresponds to DINx after 3846 SCKI clocks from power-on. If the synchronization is not held, the internal reset

is not released, and both operating modes are maintained at reset and power-down states. After synchronization

forms again, the DAC returns to normal operation with the previous sequences.

Figure 21 illustrates a timing diagram at the external reset. RST accepts an externally-forced reset with RST low,

and provides a device reset and power-down state that achieves the lowest power dissipation state available in

the PCM1691. If RST goes from high to low under synchronization among SCKI, BCK, and LRCK, the internal

reset is asserted, all registers and memory are reset, and finally, the PCM1691 enters into all power-down states.

At the same time, VOUTx is immediately forced into the AGND1 level. To begin normal operation again, toggle

RST high; the same power-up sequence is performed as the power-on reset shown in Figure 20.

The PCM1691 does not require particular power-on sequences for VCC and VDD; it allows VDD on and then

VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings, however,

simultaneous power-on is recommended for avoiding unexpected responses on VOUTx. Figure 20 illustrates the

response for VCC on with VDD on.

Figure 20. Power-On-Reset Timing Requirements

Figure 21. External Reset Timing Requirements

Submit Documentation Feedback

Product Folder Link(s): PCM1691

PCM1691 датащи(PDF) 16 Page - Texas Instruments

PCM1691 датащи(HTML) 16 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

датащи скачать

ссылки URL