HEF4044B datasheet(3/13 Pages) NXP

3 / 13 page

HEF4044B_6

Product data sheet

Rev. 06 — 11 November 2008

3 of 13

NXP Semiconductors

HEF4044B

Quad R/S latch with 3-state outputs

6.2 Pin description

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state.

Limiting values

[1]

For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.

[2]

For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

Table 2.

Pin description

Symbol

Description

n.c.

not connected

1S to 4S

3, 7, 11, 15

set input (active LOW)

1R to 4R

4, 6, 12, 14

reset input (active LOW)

common output enable input

VSS

ground supply voltage

1Q to 4Q

13, 9, 10, 1

3-state buffered latch output

VDD

supply voltage

Table 3.

Function table[1]

Input

Output

XXZ

latched

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

VDD

supply voltage

−0.5

+18

input voltage

−0.5

VDD + 0.5 V

IIK

input clamping current

VI < 0.5 V or VI >VDD + 0.5 V

±10

IOK

output clamping current

VO < 0.5 V or VO >VDD + 0.5 V

±10

II/O

input/output current

±10

Tstg

storage temperature

−65

+150

°C

Tamb

ambient temperature

−40

+85

°C

Ptot

total power dissipation

Tamb −40 °C to +85 °C

DIP16 package

[1] -

750

SO16 package

[2] -

500

per output

100

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