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MPC8641D датащи(PDF) 14 Page - Freescale Semiconductor, Inc |
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MPC8641D датащи(HTML) 14 Page - Freescale Semiconductor, Inc |
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14 / 140 page ![]() MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 1 14 Freescale Semiconductor Power Characteristics The maximum power dissipation for individual power supplies of the MPC8641D is shown in Table 5. Table 5. MPC8641D Individual Supply Maximum Power Dissipation 1 Component Description Supply Voltage (Volts) Power (Watts) Notes Per Core voltage Supply VDD_Core0/VDD_Core1 = 1.1 V @ 1500 MHz 21.00 Per Core PLL voltage supply AVDD_Core0/AVDD_Core1 = 1.1 V @ 1500 MHz 0.0125 Per Core voltage Supply VDD_Core0/VDD_Core1 = 1.05 V @ 1333 MHz 17.00 Per Core PLL voltage supply AVDD_Core0/AVDD_Core1 = 1.05 V @ 1333 MHz 0.0125 Per Core voltage Supply VDD_Core0/VDD_Core1 = 0.95 V @ 1000 MHz 11.50 5 Per Core PLL voltage supply AVDD_Core0/AVDD_Core1 = 0.95 V @ 1000 MHz 0.0125 5 DDR Controller I/O voltage supply D n_GVDD = 2.5 V @ 400 MHz 0.80 2 D n_GVDD = 1.8 V @ 533 MHz 0.68 2 D n_GVDD = 1.8 V @ 600 MHz 0.77 2 16-bit FIFO @ 200 MHz eTsec 1&2/3&4 Voltage Supply L/TVDD = 3.3 V 0.11 2, 3 non-FIFO eTsec n Voltage Supply L/TVDD = 3.3 V 0.08 2 x8 SerDes transceiver Supply SVDD = 1.1 V 0.70 2 x8 SerDes I/O Supply XVDD_SRDSn = 1.1 V 0.66 2 SerDes PLL voltage supply Port 1 or 2 AVDD_SRDS1/AVDD_SRDS2 = 1.1 V 0.10 Platform I/O Supply OVDD = 3.3 V 0.45 4 Platform source Supply VDD_PLAT = 1.1 V @ 600 MHz 12.00 Platform source Supply VDD_PLAT = 1.05 Vn @ 500 MHz 9.80 5 Platform source Supply VDD_PLAT = 1.05 Vn @ 400 MHz 7.70 Platform, Local Bus PLL voltage Supply AVDD_PLAT, AVDD_LB = 1.1 V 0.0125 Notes: 1. This is a maximum power supply number which is provided for power supply and board design information. The numbers are based on 100% bus utilization for each component. The components listed are not expected to have 100% bus usage simultaneously for all components. Actual numbers may vary based on activity. 2. Number is based on a per port/interface value. 3. This is based on one eTSEC port used. Since 16-bit FIFO mode involves two ports, the number will need to be multiplied by two for the total. The other eTSEC protocols dissipate less than this number per port. Note that the power needs to be multiplied by the number of ports used for the protocol for the total eTSEC port power dissipation. 4.This includes Local Bus, DUART, I2C, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, JTAG and Miscellaneous I/O voltage. 5. These power numbers are for Part Number MC8641xxx1000NX only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V. |
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