MPC8641D datasheet(122/140 Pages) FREESCALE

122 / 140 page

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 1

122

Freescale Semiconductor

System Design Information

The ratio of IH to IL is usually selected to be 10:1. The above simplifies to the following:

Solving for T, the equation becomes:

20 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8641.

20.1

System Clocking

This device includes six PLLs, as follows:

1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The

frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio

configuration bits as described in Section 18.2, “MPX to SYSCLK PLL Ratio.”

2. The dual e600 Core PLLs generate the e600 clock from the externally supplied input.

3. The local bus PLL generates the clock for the local bus.

4. There are two internal PLLs for the SerDes block.

20.2

Power Supply Design and Sequencing

20.2.1

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide independent filter circuits per PLL power supply as illustrated in Figure 64, one to each of the

AVDD type pins. By providing independent filters to each PLL the opportunity to cause noise injection

from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD type pin being supplied to minimize

noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD

type pin, which is on the periphery of the footprint, without the inductance of vias.

VH – VL = 1.986 × 10

–4 × nT

nT =

VH – VL

__________

1.986

× 10–4

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