MPC8640DEC datasheet(128/140 Pages) FREESCALE

128 / 140 page

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

128

Freescale Semiconductor

System Design Information

if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing

the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical.

The COP function of these processors allows a remote computer system (typically a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

port connects primarily through the JTAG interface of the processor, with some additional status

monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order

to fully control the processor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be

merged into these signals with logic.

The arrangement shown in Figure 67 allows the COP port to independently assert HRESET or TRST,

while ensuring that the target can drive HRESET as well.

The COP interface has a standard header, shown in Figure 67, for connection to the target system, and is

based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The

connector typically has pin 14 removed as a connector key.

The COP header adds many benefits such as breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features. An inexpensive option can be to leave

the COP header unpopulated until needed.

There is no standardized way to number the COP header shown in Figure 67; consequently, many different

pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then

left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter

clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in

Figure 67 is common to all known emulators.

For a multi-processor non-daisy chain configuration, Figure 68, can be duplicated for each processor. The

recommended daisy chain configuration is shown in Figure 69. Please consult with your tool vendor to

determine which configuration is supported by their emulator.

20.9.1 Termination of Unused Signals

If the JTAG interface and COP header will not be used, Freescale recommends the following connections:

•TRST should be tied to HRESET through a 0 k

Ω isolation resistor so that it is asserted when the

system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during

the power-on reset flow. Freescale recommends that the COP header be designed into the system

as shown in Figure 68. If this is not possible, the isolation resistor will allow future access to TRST

in case a JTAG interface may need to be wired onto the system in future debug situations.

•

Tie TCK to OVDD through a 10 kΩ resistor. This will prevent TCK from changing state and

reading incorrect data into the device.

•

No connection is required for TDI, TMS, or TDO.

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