MPC8640DEC datasheet(125/140 Pages) FREESCALE

125 / 140 page

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

125

System Design Information

If the high-speed SerDes port requires complete or partial termination, the unused pins should be

terminated as described in this section.

The following pins must be left unconnected (floating):

•SDn_TX[7:0]

The following pins must be connected to GND:

•SDn_RX[7:0]

•SDn_REF_CLK

•

SDn_REF_CLK

NOTE

It is recommended to power down the unused lane through SRDS1CR1[0:7]

(offset = 0xE_0F44.) (This prevents the oscillations and holds the receiver

output in a fixed state.) that maps to SERDES lane 0 to lane 7 accordingly.

For other directions on reserved or no-connects pins see Section 17, “Signal Listings.”

20.6

Pull-Up and Pull-Down Resistor Requirements

The MPC8640 requires weak pull-up resistors (2–10 k

Ω is recommended) on all open drain type pins.

The following pins must NOT be pulled down during power-on reset: TSEC4_TXD[4], LGPL0/LSDA10,

LGPL1/LSDWE, TRIG_OUT/READY, and D1_MSRCID[2].

The following are factory test pins and require strong pull up resistors

(100

Ω –1 kΩ) to OVDD

LSSD_MODE, TEST_MODE[0:3].The following pins require weak pull up resistors

(2–10 k

Ω) to their

specific power supplies: LCS[0:4], LCS[5]/DMA_DREQ2, LCS[6]/DMA_DACK[2],

LCS[7]/DMA_DDONE[2], IRQ_OUT, IIC1_SDA, IIC1_SCL, IIC2_SDA, IIC2_SCL, and

CKSTP_OUT.

The following pins should be pulled to ground with a 100-

Ω resistor: SD1_IMP_CAL_TX,

SD2_IMP_CAL_TX. The following pins should be pulled to ground with a 200-

Ω resistor:

SD1_IMP_CAL_RX, SD2_IMP_CAL_RX.

TSECn_TX_EN signals require an external 4.7-k

Ω pull down resistor to prevent PHY from seeing a valid

Transmit Enable before it is actively driven.

When the platform frequency is 400 MHz, TSEC1_TXD[1] must be pulled down at reset.

Partial Termination when a SerDes port is enabled through both POR input and DEVDISR is determined by

the SerDes port mode. If the port is in x8 PCI Express mode, no termination is required because all pins are

being used. If the port is in x1/x2/x4 PCI Express mode, termination is required on the unused pins. If the port

is in x4 Serial RapidIO mode termination is required on the unused pins.

If a SerDes port is enabled through the POR input and then disabled through DEVDISR, no hardware changes

are required. Termination of the SerDes port should follow what is required when the port is enabled through

both POR input and DEVDISR. See Note 1 for more information.

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