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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8640DEC датащи(PDF) 131 Page - Freescale Semiconductor, Inc |
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MPC8640DEC датащи(HTML) 131 Page - Freescale Semiconductor, Inc |
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131 / 140 page  MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 131 Ordering Information Figure 69. JTAG/COP Interface Connection for Multiple MPC8640 Devices in Daisy Chain Configuration 21 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Section 21.1, “Part Numbers Fully Addressed by This Document.” COP_SRESET COP_TRST COP_HRESET JTAG/COP SRESET1 SRESET0 TDI Header HRESET TRST CHKSTP_OUT CHKSTP_IN TMS TCK TDO 10k Ω 10k Ω SRESET1 HRESET From Target Board Sources (if any) COP_TDI 11 13 3 COP_CHKSTP_OUT COP_CHKSTP_IN SRESET1 SRESET0 TDI TRST CHKSTP_OUT CHKSTP_IN TMS TCK TDO 4 15 8 COP_TMS 2 10 COP_TCK GND 14 9 7 6 NC NC COP_VDD_SENSE 16 COP_TDO 1 3 12 2 HRESET OVDD SRESET0 4 4 4 4 10k Ω Notes: 1. Populate this with a 10 Ω resistor for short circuit/current-limiting protection. 2. KEY location; pin 14 is not physically present on the COP header. 3. Use a AND gate with sufficient drive strength to drive two inputs. 4. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown above. 10k Ω 10k Ω 10k Ω 10k Ω 10k Ω 10k Ω 10k Ω 6 5 10 Ω MPC8640 MPC8640 3 5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed. 6. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity. 5 NC 1 OVDD |
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