MPC8640DEC datasheet(123/140 Pages) FREESCALE

123 / 140 page

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

123

System Design Information

20.2.2

PLL Power Supply Sequencing

For details on power sequencing for the AVDD type and supplies refer to Section 2.2, “Power Up/Down

Sequence.”

20.3

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8640 system, and the device

itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system

designer place at least one decoupling capacitor at each OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren,

and VDD_PLAT pin of the device. These decoupling capacitors should receive their power from separate

OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren, and VDD_PLAT and GND power planes in the PCB,

utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a

standard escape pattern. Others may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren, and VDD_PLAT planes, to enable quick

recharging of the smaller chip capacitors. They should also be connected to the power and ground planes

through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum

or Sanyo OSCON).

20.4

SerDes Block Power Supply Decoupling Recommendations

The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD_SRDSn) to ensure

low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is

outlined below.

Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections

from all capacitors to power and ground should be done with multiple vias to further reduce inductance.

•

First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible

to the supply balls of the device. Where the board has blind vias, these capacitors should be placed

directly below the chip supply and ground connections. Where the board does not have blind vias,

these capacitors should be placed in a ring around the device as close to the supply and ground

connections as possible.

•

Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be

done for all SerDes supplies.

•

Third, between the device and any SerDes voltage regulator there should be a 10-µF, low

equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT

tantalum chip capacitor. This should be done for all SerDes supplies.

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