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MPC5533 датащи(PDF) 42 Page - Freescale Semiconductor, Inc |
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MPC5533 датащи(HTML) 42 Page - Freescale Semiconductor, Inc |
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42 / 50 page ![]() MPC5533 Microcontroller Data Sheet, Rev. 0.0 Electrical Characteristics Freescale Semiconductor 42 3.13.8 eQADC SSI Timing Figure 23. EQADC SSI Timing Table 26. EQADC SSI Timing Characteristics Spec Rating Symbol Minimum Typical Maximum Unit 2 FCK period (tFCK = 1 ÷ fFCK) 1, 2 1 SS timing specified at V DDEH = 3.0–5.25 V, TA = TL to TH, and CL = 25 pF with SRC = 0b11. Maximum operating frequency varies depending on track delays, master pad delays, and slave pad delays. 2 FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number. tFCK 2— 17 tSYS_CLK 3 Clock (FCK) high time tFCKHT tSYS_CLK − 6.5 — 9 × (t SYS_CLK + 6.5) ns 4 Clock (FCK) low time tFCKLT tSYS_CLK − 6.5 — 8 × (t SYS_CLK + 6.5) ns 5 SDS lead / lag time tSDS_LL –7.5 — +7.5 ns 6 SDO lead / lag time tSDO_LL –7.5 — +7.5 ns 7 EQADC data setup time (inputs) tEQ_SU 22 — — ns 8 EQADC data hold time (inputs) tEQ_HO 1— — ns 1st (MSB) 2nd 25th 26th 1st (MSB) 2nd 25th 26th 8 7 5 6 4 5 4 2 3 FCK SDS SDO External device data sample at SDI EQADC data sample at FCK falling-edge FCK rising-edge |
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