MPC5533 datasheet(37/50 Pages) FREESCALE

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Electrical Characteristics

MPC5533 Microcontroller Data Sheet, Rev. 0.0

Freescale Semiconductor

3.13.7

DSPI Timing

Table 25. DSPI Timing 1, 2

1 All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of

S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0–5.25 V, TA = TL to TH, and

CL = 50 pF with SRC = 0b11.

Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).

42 MHz parts allow for 40 MHz system clock + 2% FM; 68 MHz parts allow for a 66 MHz system clock + 2% FM, and

82 MHz parts allow for 80 MHz system clock + 2% FM.

Spec

Characteristic

Symbol

40 MHz

66 MHz

80 MHz

Unit

Min.

Max

Min.

Max

Min.

Max

SCK cycle time 3, 4

3 The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.

These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.

4 The actual minimum SCK cycle time is limited by pad performance.

tSCK

48.8 ns

5.8 ms

28.4 ns

3.5 ms

24.4 ns

2.9 ms

—

PCS to SCK delay5

5 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].

tCSC

—26

—

—ns

After SCK delay6

6 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

tASC

—25

—

—ns

SCK duty cycle

tSDC

(tSCK ÷ 2)

– 2 ns

(tSCK ÷ 2)

+ 2 ns

(tSCK ÷ 2)

– 2 ns

(tSCK ÷ 2)

+ 2 ns

(tSCK ÷ 2)

– 2 ns

(tSCK ÷ 2)

+ 2 ns

Slave access time

(SS active to SOUT driven)

—

Slave SOUT disable time

(SS inactive to SOUT Hi-Z, or

invalid)

tDIS

—

7PCSx to PCSS time

tPCSC

—4

—

—ns

8PCSS to PCSx time

tPASC

—5

—

—ns

Data setup time for inputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)7

Master (MTFE = 1, CPHA = 1)

7 This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.

tSUI

–4

—

Data hold time for inputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)7

Master (MTFE = 1, CPHA = 1)

tHI

–4

—

–4

—

–4

—

Data valid (after SCK edge)

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

tSUO

—

Data hold time for outputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

tHO

–5

5.5

–5

—

–5

5.5

–5

—

–5

5.5

–5

—

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