MPC5121E datasheet(35/86 Pages) FREESCALE

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Electrical and Thermal Characteristics

MPC5121E/MPC5123 Data Sheet, Rev. 1

Freescale Semiconductor

For Measurement and Test Conditions, see the PCI Local Bus Specification.

3.3.7

LPC

The Local Plus Bus is the external bus interface of the MPC5121e/MPC5123. A maximum of eight configurable chip selects

(CS) are provided. There are two main modes of operation: non-MUXed and MUXED. The reference clock is the LPC CLK.

The maximum bus frequency is 83 MHz.

Definition of Acronyms and Terms:

WS = Wait State

DC = Dead Cycle

HC = Hold Cycle

DS = Data Size in Bytes

BBT = Burst Bytes per Transfer

AL = Address latch enable Length

ALT = Chip select/Address Latch Timing

tLPCck = LPC clock period

Table 22. PCI Timing Parameters1

1 See the timing measurement conditions in the PCI Local Bus Specification. It is important that all driven

signal transitions drive to their Voh or Vol level within one Tcyc.

Sym

Description

66 MHz

33 MHz

Units

SpecID

Min2

2 Minimum times are measured at the package pin with the load circuit, and maximum times are measured

with the load circuit as shown in the PCI Local Bus Specification.

Max

Min

Max

tval

CLK to Signal Valid Delay –

bused signals1,2,3

262

A6.5

tval(ptp) CLK to Signal Valid Delay – point

to point1,2,3

262

A6.6

ton

Float to Active Delay1

2—2—

A6.7

toff

Active to Float Delay1

A6.8

tsu

Input Setup Time to CLK – bused

signals3,4

3—7—

A6.9

tsu(ptp) Input Setup Time to CLK – point

to point3,4

3 REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT#

and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused.

—

10,12

—

A6.10

Input Hold Time from CLK4

4 See the timing measurement conditions in the PCI Local Bus Specification.

0—0—

A6.11

Preliminary

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