MPC5121E datasheet(32/86 Pages) FREESCALE

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MPC5121E/MPC5123 Data Sheet, Rev. 1

Electrical and Thermal Characteristics

Freescale Semiconductor

3.3.5.1

DDR and DDR2 SDRAM AC Timing Specifications

Notes:

1. Measured with clock pin loaded with differential 100 ohm termination resistor.

2. Measured with all outputs except the clock loaded with 50 ohm termination resistor to VDD_IO_MEM/2.

3. All transitions measured at mid-supply (VDD_IO_MEM/2)

4. In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low.

5. Window position is given for tDQSEN = 2.0 tCK. For other values of tDQSEN, window position is shifted accordingly.

Figure 7 shows the DDR SDRAM write timing.

Table 20. DDR and DDR2 (DDR2-400) SDRAM Timing Specifications

At recommended operating conditions with VDD_MEM_IO of

±5%

Parameter

Symbol

Min

Max

Unit

Notes

SpecID

Clock cycle time, CL=x

tCK

5000

—

A5.1

MCK AC differential crosspoint

voltage

VIX-AC

VDD_IO_MEM*0.5

- 0.1

VDD_IO_MEM * 0.5

+ 0.1

A5.2

CK HIGH pulse width

tCH

0.47

0.53

tCK

1,3

A5.3

CK LOW pulse width

tCL

0.47

0.53

tCK

1,3

A5.4

Skew between MCK and DQS

transitions

tDQSS

−0.25

0.25

tCK

2,3

A5.5

Address and control output setup

time relative to MCK rising edge

tOS(base)

tCK/2 - 750

—

2,3

A5.6

Address and control output hold

time relative to MCK rising edge

tOH(base)

tCK/2 - 750

—

2,3

A5.7

DQ and DM output setup time

relative to DQS

tDS1(base)

tCK/4 - 500

—

2,3

A5.8

DQ and DM output hold time relative

to DQS

tDH1(base)

tCK/4 - 500

—

2,3

A5.9

DQS-DQ skew for DQS and

associated DQ inputs

tDQSQ

- tCK/4 - 600

tCK/4 - 600

A5.10

DQS window start position related to

CAS read command

tDQSEN

TBD

1,2,3,4,5

A5.11

Preliminary

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