ADF9010BCPZ datasheet(13/28 Pages) AD

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ADF9010

Rev. 0 | Page 13 of 28

PFD and Charge Pump

The phase frequency detector (PFD) takes inputs from the

R counter and N counter (N = BP + A) and produces an output

proportional to the phase and frequency difference between

them (see Figure 15).

DELAY

CLR2

CLR1

CHARGE

PUMP

DOWN

RDIVIDER

NDIVIDER

CP OUTPUT

R DIVIDER

N DIVIDER

CPGND

Figure 15. PFD Simplified Schematic and Timing (In Lock)

MUXOUT

The output multiplexer on the ADF9010 allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 in the control

latch. The full truth table is shown in Figure 22. Figure 16

shows the MUXOUT section in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect:

digital and analog. Digital lock detect is active high. If the LDP

in the R counter latch is set to 0, digital lock detect is set high

when the phase error on three consecutive phase detector cycles

is less than 15 ns.

With the LDP set to 1, five consecutive cycles of less than 15 ns

phase error are required to set the lock detect. It stays set high

until a phase error of greater than 25 ns is detected on any

subsequent PD cycle.

The N-channel open-drain analog lock detect should be

operated with an external pull-up resistor of 10 kΩ nominal.

When a lock has been detected, this output is high with narrow

low-going pulses.

R COUNTER OUTPUT

N COUNTER OUTPUT

DIGITAL LOCK DETECT

DGND

CONTROL

MUX

MUXOUT

DVDD

ANALOG LOCK DETECT

SDOUT

Figure 16. MUXOUT Circuit

Voltage-Controlled Oscillator (VCO)

The VCO core in the ADF9010 uses 16 overlapping bands, as

shown in Figure 17, to allow a wide frequency range to be covered

with a low VCO sensitivity (KV) and to result in good phase noise

and spurious performance. The VCO operates at 4× the LO

frequency, providing an output range of 840 MHz to 960 MHz.

The correct band is chosen automatically by the band select

logic at power-up or whenever the LO latch is updated. During

band select, which takes five PFD cycles, the VCO VTUNE is

disconnected from the output of the loop filter and connected

to an internal reference voltage.

3.5

3.0

2.5

1.5

1.0

0.5

750

800

850

SERIES 1

900

950

1000

FREQUENCY (Hz)

Figure 17. VCO Bands

The R counter output is used as the clock for the band select logic

and should not exceed 1 MHz. A programmable divider is pro-

vided at the R counter input to allow division by 1, 2, 4, or 8 and

is controlled by Bit BSC1 and Bit BSC2 in the Tx latch. Where the

required PFD frequency exceeds 1 MHz, the divide ratio should be

set to allow enough time to select the correct band.

After the band is selected, normal PLL action resumes. The

nominal value of KV is 32 MHz/V or 8 MHz/V, taking into

account the divide by 4.

The output from the VCO is divided by 4 for the LO inputs to

the mixers, and for the LO output drive to the demodulator.

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