AD9783-EBZ datasheet(26/36 Pages) AD

26 / 36 page

AD9780/AD9781/AD9783

Rev. A | Page 26 of 36

CH1 100mV

A CH1

58mV

125ps/DIV 2.12ns

20GSPS IT 2.5ps/PT

V1: 296mV

V2: –228mV

ΔV: –524mV

Figure 58. Eye Diagram of Data Source Used in Building the 600 MHz Timing

Data Array of Table 14

Over temperature, the valid sampling window shifts. Therefore,

when attempting operation of the device over 500 MHz, the

timing must be optimized again whenever the device undergoes

a temperature change of more than 20oC. Another consideration

in the timing of the digital data port is the propagation delay

variation from the clock output (DCOP/DCON) to the clock

input. If this varies significantly over time (more than 25% of

SET or HLD) due to temperature changes or other effects,

repeat this timing calibration procedure.

At sample rates of ≤400 MSPS, the interface timing margin is

sufficient to allow for a simplified procedure. In this case, the

SEEK bit can be recorded as SMP is swept through the range

from 0 to 31. The center of the first valid sampling window can

then be chosen as the optimal value of SMP. Using the 400 MHz

case from Table 14 as an example, the first valid sampling

window occurs for SMP values of 7 to 13. The center of this

window is 10, so 10 can be used as the optimal SMP value.

DRIVING THE CLK INPUT

The CLK input requires a low jitter differential drive signal. It is

a PMOS input differential pair powered from the 1.8 V supply;

therefore, it is important to maintain the specified 400 mV

input common-mode voltage. Each input pin can safely swing

from 200 mV p-p to 1 V p-p about the 400 mV common-mode

voltage. While these input levels are not directly LVDS-compatible,

CLK can be driven by an offset ac-coupled LVDS signal, as

shown in Figure 59.

LVDS_P_IN

CLKP

50Ω

0.1µF

LVDS_N_IN

CLKN

VCM = 400mV

Figure 59. LVDS DAC CLK Drive Circuit

If a clean sine clock is available, it can be transformer-coupled

to CLKP and CLKN as shown in Figure 60. Use of a CMOS or

TTL clock is also acceptable for lower sample rates. It can be

routed through a CMOS-to-LVDS translator, and then ac-

coupled, as described in this section. Alternatively, it can be

transformer-coupled and clamped, as shown in Figure 60.

50Ω

TTL OR CMOS

CLK INPUT

CLKP

CLKN

VCM = 400mV

BAV99ZXCT

HIGH SPEED

DUAL DIODE

0.1µF

Figure 60. TTL or CMOS DAC CLK Drive Circuit

A simple bias network for generating the 400 mV common-

mode voltage is shown in Figure 61. It is important to use

CVDD18 and CGND for the clock bias circuit. Any noise or

other signal coupled onto the clock is multiplied by the DAC

digital input signal and can degrade the DAC’s performance.

0.1µF

1nF

VCM = 400mV

CVDD18

CGND

1kΩ

287Ω

1nF

Figure 61. DAC CLK VCM Generator Circuit

FULL-SCALE CURRENT GENERATION

Internal Reference

Full-scale current on the I DAC and Q DAC can be set from

8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is

used to set up a current in an external resistor connected to

FS ADJ (Pin 54). A simplified block diagram of the reference

circuitry is shown in Figure 62. The recommended value for

the external resistor is 10 kΩ, which sets up an IREFERENCE in the

resistor of 120 μA, which in turn provides a DAC output full-

scale current of 20 mA. Because the gain error is a linear function

of this resistor, a high precision resistor improves gain matching

to the internal matching specification of the devices. Internal

current mirrors provide a current-gain scaling, where I DAC or

Q DAC gain is a 10-bit word in the SPI port register. The default

value for the DAC gain registers gives a full-scale current output

(IFS) of approximately 20 mA, where IFS is equal to

IFS = (86.6 + (0.220 × DAC gain)) × 1000/R

CURRENT

SCALING

1.2V BAND GAP

I DAC GAIN

Q DAC GAIN

AD9783

I DAC

Q DAC

DAC FULL-SCALE

REFERENCE CURRENT

REFIO

FS ADJ

0.1µF

10kΩ

Figure 62. Reference Circuitry

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