AD9783-EBZ datasheet(25/36 Pages) AD

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AD9780/AD9781/AD9783

Rev. A | Page 25 of 36

Building the Array

The following procedure is used to build the array:

Set the values of SMP, SET, and HLD to 0. Read and record

the value of the SEEK bit.

With SMP and SET set to 0, increment the HLD value until

the SEEK bit toggles, and then record the HLD value. This

measures the hold time as shown in Figure 57.

With SMP and HLD set to 0, increment the SET value until

the SEEK bit toggles, and then record the SET value. This

measures the setup time as shown in Figure 57.

Set the value of SET and HLD to 0. Increment the value of

SMP and record the value of the SEEK bit.

Increment HLD until the SEEK bit toggles, and then record

the HLD value. Set HLD to 0 and increment SET until the

SEEK bit toggles, and then record the SET value.

Repeat Step 4 and Step 5 until the procedure has been

completed for SMP values from 0 to 31.

Note that while building the table, a value for either SET or

HLD may not be found to make the SEEK bit toggle. In this

case, assume a value of 15.

Table 14. Timing Data Arrays

fDACCLK = 200 MHz

fDACCLK = 400 MHz

fDACCLK = 600 MHz

SMP

SEEK

SET

HLD

SEEK

SET

HLD

SEEK

SET

HLD

Table 14 shows example arrays taken at DAC sample rates of

200 MHz, 400 MHz, and 600 MHz. It should be noted that the

delay from the DCO input to the DCI output of the data source

has a profound effect on when the SEEK bit toggles over the

range of SMP values. Therefore, the tables generated in any

particular system do not necessarily match the example timing

data arrays in Table 14.

As may be seen in Table 14, at 600 MHz the device has only two

working SMP settings. There is no way to monitor timing

margin in real time, so the output must be interrupted to check

or correct timing errors. The device should therefore not be

clocked above 500 MHz in applications where 100% up time is a

requirement.

Determining the SMP Value

Once the timing data array has been built, the value of SMP can

be determined using the following procedure:

Look for the SMP value that corresponds to the 0-to-1

transition of the SEEK bit in the table. In the 600 MHz case

from Table 14, this occurs for an SMP value of 6.

Look for the SMP value that corresponds to the 1-to-0

transition of the SEEK bit in the table. In the 600 MHz case

from Table 14, this occurs for an SMP value of 11.

The same two values found in Step 1 and Step 2 indicate

the valid sampling window. In the 500 MHz case, this

occurs for an SMP value of 11.

The optimal SMP value in the valid sampling window is

where the following two conditions are true: SET < HLD

and |HLD − SET| is the smallest value.

In the 600 MHz case, the optimal SMP value is 7.

After programming the calculated value of SMP (referred to as

SMPOPTIMAL), the configuration should be tested to verify that

there is sufficient timing margin. This can be accomplished by

ensuring that the SEEK bit reads back as a 1 for SMP values

equal to SMPOPTIMAL + 1 and SMPOPTIMAL − 1. Also, it should be

noted that the sum of SET and HLD should be a minimum of 8.

If the sum is lower than this, you should check for excessive jitter

on the clock input line and check that the frequency of the clock

input does not exceed the data sheet maximum of 500 MHz (or

1000 Mbps).

As mentioned previously, low jitter and skew between the input

data bits and DCI are critical for reliable operation at the maxi-

mum input data rates. Figure 58 shows the eye diagram for the

input data signals that were used to collect the data in Table 14.

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