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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9522-1/PCBZ датащи(PDF) 10 Page - Analog Devices |
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AD9522-1/PCBZ датащи(HTML) 10 Page - Analog Devices |
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10 / 84 page  AD9522-1 Rev. 0 | Page 10 of 84 CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter Min Typ Max Unit Test Conditions/Comments LVDS ABSOLUTE PHASE NOISE Internal VCO; VCO divider = 4; LVDS output and for loop bandwidths < 1 kHz VCO = 2650 MHz; Output = 662.5 MHz @ 1 kHz Offset −59 dBc/Hz @ 10 kHz Offset −90 dBc/Hz @ 100 kHz Offset −116 dBc/Hz @ 1 MHz Offset −134 dBc/Hz @ 10 MHz Offset −147 dBc/Hz @ 40 MHz Offset −150 dBc/Hz VCO = 2460 MHz; Output = 615 MHz @ 1 kHz Offset −62 dBc/Hz @ 10 kHz Offset −92 dBc/Hz @ 100 kHz Offset −118 dBc/Hz @ 1 MHz Offset −136 dBc/Hz @ 10 MHz Offset −149 dBc/Hz @ 40 MHz Offset −151 dBc/Hz VCO = 2270 MHz; Output = 567.5 MHz @ 1 kHz Offset −65 dBc/Hz @ 10 kHz Offset −95 dBc/Hz @ 100 kHz Offset −121 dBc/Hz @ 1 MHz Offset −138 dBc/Hz @ 10 MHz Offset −149 dBc/Hz @ 40 MHz Offset −151 dBc/Hz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter Min Typ Max Unit Test Conditions/Comments LVDS OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R DIV = 1 VCO = 2458 MHz; LVDS = 245.76 MHz; PLL LBW = 55 kHz 158 fs rms Integration BW = 200 kHz to 10 MHz 323 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2458 MHz; LVDS = 122.88 MHz; PLL LBW = 55 kHz 162 fs rms Integration BW = 200 kHz to 10 MHz 323 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2458 MHz; LVDS = 61.44 MHz; PLL LBW = 55 kHz 210 fs rms Integration BW = 200 kHz to 10 MHz 371 fs rms Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9. Parameter Min Typ Max Unit Test Conditions/Comments LVDS OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 19.44 MHz; R DIV = 162 VCO = 2333 MHz; LVDS = 155.52 MHz; PLL LBW = 1.8 kHz 491 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2458 MHz; LVDS = 122.88 MHz; PLL LBW = 1.8 kHz 554 fs rms Integration BW = 12 kHz to 20 MHz |
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