AD7682 datasheet(20/28 Pages) AD

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AD7949

Rev. A | Page 20 of 28

POWER SUPPLY

The AD7949 uses three power supply pins: two core supplies

(VDD) and a digital input/output interface supply (VIO). VIO

allows direct interface with any logic between 1.8 V and VDD.

To reduce the supplies needed, the VIO and VDD pins can be

tied together. The AD7949 is independent of power supply

sequencing between VIO and VDD. The only restriction is that

CNV must be low during power up. Additionally, it is very

insensitive to power supply variations over a wide frequency

range, as shown in Figure 30.

10k

100

FREQUENCY (kHz)

Figure 30. PSRR vs. Frequency

The AD7949 powers down automatically at the end of each

conversion phase; therefore, the operating currents and power

scale linearly with the sampling rate. This makes the part ideal

for low sampling rates (even of a few hertz) and low battery-

powered applications.

10000

1000

100

0.1

0.010

0.001

100

10k

100k

SAMPLING RATE (sps)

VDD = 5V, INTERNAL REF

VDD = 5V, EXTERNAL REF

VDD = 2.5V, EXTERNAL REF

VIO

Figure 31. Operating Currents vs. Sampling Rate

SUPPLYING THE ADC FROM THE REFERENCE

For simplified applications, the AD7949, with its low operating

current, can be supplied directly using the reference circuit as

shown in Figure 32. The reference line can be driven by

•

The system power supply directly

•

A reference voltage with enough current output capability,

such as the ADR43x/ADR44x

•

A reference buffer, such as the AD8605, which can also

filter the system power supply, as shown in Figure 32

AD8605

AD7949

VIO

REF

VDD

10µF

1µF

0.1µF

10Ω

10kΩ

1µF

1OPTIONAL REFERENCE BUFFER AND FILTER.

0.1µF

Figure 32. Example of an Application Circuit

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