AD7682 datasheet(7/28 Pages) AD

номер детали	AD7682

подробное описание детали	14-Bit, 8-Channel, 250 kSPS PulSAR ADC

PDF	28 Pages

Scroll/Zoom	100%

производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

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7 / 28 page

AD7949

Rev. A | Page 7 of 28

VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.

Table 4. 1

Parameter

Symbol

Min

Typ

Max

Unit

Conversion Time: CNV Rising Edge to Data Available

tCONV

3.2

μs

Acquisition Time

tACQ

1.8

μs

Time Between Conversions

tCYC

μs

CNV Pulse Width

tCNVH

Data Write/Read During Conversion

tDATA

1.0

μs

SCK Period

tSCK

SCK Low Time

tSCKL

SCK High Time

tSCKH

SCK Falling Edge to Data Remains Valid

tHSDO

SCK Falling Edge to Data Valid Delay

tDSDO

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

CNV Low to SDO D15 MSB Valid

tEN

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

CNV High or Last SCK Falling Edge to SDO High Impedance

tDIS

CNV Low to SCK Rising Edge

tCLSCK

SDI Valid Setup Time from SCK Falling Edge

tSDIN

SDI Valid Hold Time from SCK Falling Edge

tHDIN

1 See Figure 2 and Figure 3 for load conditions.

IOL

500µA

IOH

1.4V

TOSDO

50pF

Figure 2. Load Circuit for Digital Interface Timing

30% VIO

70% VIO

2V OR VIO – 0.5V1

0.8V OR 0.5V2

2V OR VIO – 0.5V1

tDELAY

1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 3. Voltage Levels for Timing

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