AD7352

Rev. 0 | Page 16 of 20

FULL POWER-DOWN MODE

Full power-down mode is intended for use in applications

where throughput rates slower than those in partial power-

down mode are required because power-up from a full power-

down takes substantially longer than that from a partial power-

down. This mode is more suited to applications in which a

series of conversions performed at a relatively high throughput

rate are followed by a long period of inactivity and, thus, power-

down. When the AD7352 is in full power-down mode, all

analog circuitry is powered down including the on-chip

reference and reference buffers. Full power-down mode is

entered in a similar way as partial power-down mode, except

that the timing sequence shown in Figure 25 must be executed

twice. The conversion process must be interrupted in a similar

fashion by bringing CS high anywhere after the second falling

device enters partial power-down mode at this point.

To reach full power-down mode, the next conversion cycle must

be interrupted in the same way, as shown in Figure 27. When

CS is brought high in this window of SCLKs, the part fully

powers down. Note that it is not necessary to complete the 14 or

16 SCLKs once CS has been brought high to enter a power-

down mode.

To exit full power-down mode and power-up the AD7352,

perform a dummy conversion, similar to powering up from

partial power-down. On the falling edge of CS, the device begins to

power up as long as CS is held low until after the falling edge of

a conversion can be initiated, as shown in

.

Figure 28

SCLK

CS

INVALID DATA

VALID DATA

110

14

14

1

THE PART BEGINS

TO POWER UP.

THE PART IS FULLY POWERED UP;

SEE THE POWER-UP TIMES SECTION.

Figure 26. Exiting Partial Power-Down Mode

THREE-STATE

110

14

2

SCLK

CS

THREE-STATE

110

2

INVALID DATA

INVALID DATA

THE PART BEGINS

TO POWER UP.

THE PART ENTERS

PARTIAL POWER-DOWN MODE.

THE PART ENTERS

FULL POWER-DOWN MODE.

14

Figure 27. Entering Full Power-Down Mode

SCLK

INVALID DATA

VALID DATA

1

10

14

14

1

THE PART BEGINS

TO POWER UP.

CS

THE PART IS FULLY POWERED UP;

SEE THE POWER-UP TIMES SECTION.

Figure 28. Exiting Full Power-Down Mode