AD5590BBCZ datasheet(27/44 Pages) AD

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AD5590

Rev. 0 | Page 27 of 44

ADC SECTION

The ADC section is a fast, 16-channel, 12-bit, single-supply,

analog-to-digital converter. The ADC is capable of throughput

rates of up to 1 MSPS when provided with a 20 MHz clock.

The ADC section provides the user with an on-chip track-

and-hold, analog-to-digital converter. The ADC section has

16 single-ended input channels with a channel sequencer,

allowing the user to select a sequence of channels through

which the ADC can cycle with each consecutive ASYNC falling

edge. The serial clock input accesses data from the ADC, controls

the transfer of data written to the ADC, and provides the clock

source for the successive approximation ADC converter. The

analog input range for the ADC is 0 V to VREFA or 0 V to 2 ×

VREFA depending on the status of Bit 1 in the control register.

The ADC provides flexible power management options to

allow the user to achieve the best power performance for a

given throughput rate. These options are selected by program-

ming the power management bits in the ADC control register.

ADC CONVERTER OPERATION

The ADC is a 12-bit successive approximation analog-to-digital

converter based around a capacitive DAC. The ADC can convert

analog input signals in the range 0 V to VREFA or 0 V to 2 × VREFA.

Figure 54 and Figure 55 show simplified schematics of the ADC.

The ADC comprises control logic, SAR, and a capacitive DAC,

which are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator back

into a balanced condition. Figure 54 shows the ADC during

its acquisition phase. SW2 is closed and SW1 is in Position

A. The comparator is held in a balanced condition and the

sampling capacitor acquires the signal on the selected VIN

channel.

VIN0

VIN15

ADCGND

SW1

SW2

4kΩ

COMPARATOR

CAPACITIVE

DAC

CONTROL

LOGIC

Figure 54. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 55), SW2 opens

and SW1 moves to Position B, causing the comparator to become

unbalanced. The control logic and the capacitive DAC are used

to add and subtract fixed amounts of charge from the sampling

capacitor to bring the comparator back into a balanced condi-

tion. When the comparator is rebalanced, the conversion is

complete. The control logic generates the ADC output code.

Figure 57 shows the ADC transfer function.

VIN0

VIN15

ADCGND

SW1

SW2

4kΩ

COMPARATOR

CAPACITIVE

DAC

CONTROL

LOGIC

Figure 55. ADC Conversion Phase

Analog Input

Figure 56 shows an equivalent circuit of the analog input structure

of the ADC. The two diodes, D1 and D2, provide ESD protection

for the analog inputs. Care must be taken to ensure that the analog

input signal never exceed the supply rails by more than 200 mV.

This causes these diodes to become forward biased and start

conducting current into the substrate. 10 mA is the maximum

current these diodes can conduct without causing irreversible

damage to the ADC. Capacitor C1 in Figure 56 is typically about

4 pF and can primarily be attributed to pin capacitance. Resistor

R1 is a lumped component made up of the on resistance of a

switch (track-and-hold switch) and also includes the on resis-

tance of the input multiplexer.

4pF

VINx

CONVERSION PHASE—SWITCH OPEN

TRACK PHASE—SWITCH CLOSED

ADCVDD

30pF

Figure 56. Equivalent Analog Input Circuit

The total resistance is typically about 400 Ω. Capacitor C2 is

the ADC sampling capacitor and typically has a capacitance of

30 pF. For ac applications, removing high frequency components

from the analog input signal is recommended by use of an RC

low-pass filter on the relevant analog input pin. In applications

where harmonic distortion and signal-to-noise ratio are critical,

drive the analog input from a low impedance source. Large

source impedances significantly affect the ac performance of

the ADC. This may necessitate the use of an input buffer

amplifier. The choice of the op amp is a function of the

particular application.

When no amplifier is used to drive the analog input, limit the

source impedance to low values. The maximum source impedance

depends on the amount of total harmonic distortion (THD) that

can be tolerated. The THD increases as the source impedance

increases, and performance degrades (see Figure 28).

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