AD5590

Rev. 0 | Page 37 of 44

ADC Control Register

The control register on the ADC is a 12-bit, write-only register.

Data is loaded from the ADIN pin of the ADC on the falling

edge of ASCLK. The data is transferred on the ADIN line at the

same time as the conversion result is read from the ADC. The

data transferred on the ADIN line corresponds to the ADC

configuration for the next conversion. This requires 16 serial

clocks for every data transfer. Only the information provided

on the first 12 falling clock edges (after ASYNC falling edge) is

loaded to the ADC control register. MSB denotes the first bit

in the data stream. The bit functions are outlined in

.

Writing of information to the ADC control register takes place

on the first 12 falling edges of ASCLK in a data transfer, assuming

the MSB, that is, the write bit, has been set to 1. If the ADC

control register is programmed to use the shadow register,

writing of information to the shadow register takes place on

all 16 ASCLK falling edges in the next serial transfer (see

). The shadow register is updated on the rising edge

of

Table 21

Figure 72

ASYNC and the track-and-hold begins to track the first

channel selected in the sequence.

If the weak/TRI bit in the ADC control register is set to 1, rather

edge, the ADOUT line is instead pulled weakly to the logic level

corresponding to ADD3 of the next serial transfer. This is done

to ensure that the MSB of the next serial transfer is set up in

time for the first ASCLK falling edge after the ASYNC falling

edge. If the weak/TRI bit is set to 0 and the ADOUT line has

been in true three-state between conversions, then depending

on the particular DSP or microcontroller interfacing to the

ADC, the ADD3 address bit may not be set up in time for the

DSP/microcontroller to clock it in successfully. In this case,

ADD3 is only driven from the falling edge of ASYNC and must

then be clocked in by the DSP on the following falling edge of

ASCLK. However, if the weak/TRI bit had been set to 1, then

although ADOUT is driven with the ADD3 address bit from

the last conversion, it is nevertheless so weakly driven that

another device may still take control of the bus. It does not lead

to a bus contention (for example, a 10 kΩ pull-up or pull-down

resistor would be sufficient to overdrive the logic level of ADD3

between conversions), and all 16 channels may be identified.

However, if this does happen and another device takes control

of the bus, it is not guaranteed that ADOUT becomes fully

driven to ADD3 again in time for the read operation when

control of the bus is taken back.

This is especially useful if using an automatic sequence mode

to identify to which channel each result corresponds. Obviously,

if only the first eight channels are in use, the ADD3 address bit

does not need to be decoded, and whether it is successfully clocked

in as a 1 or 0 does not matter as long as it is still counted by the

DSP/microcontroller as the MSB of the 16-bit serial transfer.

Table 21. ADC Control Register

MSB

LSB

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Write

SEQ

ADD3

ADD2

ADD1

ADD0

PM1

PM0

Shadow

Weak/TRI

Range

Coding

Table 22. ADC Control Register Bit Functions

Bit

Name

Description

11

Write

The value written to this bit of the control register determines whether the following 11 bits are loaded to the control

register or not. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, the remaining 11 bits

are not loaded to the control register, therefore it remains unchanged.

10

SEQ

The SEQ bit in the control register is used in conjunction with the shadow bit to control the use of the sequencer

function and to access the shadow register (see Table 25).

9:6

ADD3:ADD0

These four address bits are loaded at the end of the current conversion sequence and select which analog input

channel is to be converted on in the next serial transfer, or can select the final channel in a consecutive sequence, as

described in Table 25. The selected input channel is decoded as shown in Table 23. The address bits corresponding to

the conversion result are also output on ADOUT prior to the 12 bits of data (see the Serial Interface section). The next

5, 4

PM1, PM0

These two power management bits decode the mode of operation of the ADC, as shown in Table 24.

3

Shadow

The shadow bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer

function and access the shadow register (see Table 25).

2

Weak/TRI

This bit selects the state of the ADOUT line at the end of the current serial transfer. If it is set to 1, the ADOUT line is

weakly driven to the ADD3 channel address bit of the ensuing conversion. If this bit is set to 0, ADOUT returns to three-

state at the end of the serial transfer. See the Serial Interface section for more details.

1

Range

This bit selects the analog input range to be used on the ADC. If it is set to 0, then the analog input range extends from

0

Coding

This bit selects the type of output coding the ADC uses for the conversion result. If this bit is set to 0, the output coding

for the ADC is twos complement. If this bit is set to 1, the output coding from the ADC is straight binary (for the next

conversion).