M38044FFHKP datasheet(325/387 Pages) RENESAS

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3-35

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.3 Notes on use

(2)

START condition generating procedure using multi-master

➀ Procedure example (The necessary conditions of the generating procedure are described as the

following ➁ to ➄).

LDA #SLADR

(Taking out of slave address value)

SEI

(Interrupt disabled)

BBS 5, S1, BUSBUSY (BB flag confirming and branch process)

BUSFREE:

STA S0

(Writing of slave address value)

LDM #$F0, S1

(Trigger of START condition generating)

CLI

(Interrupt enabled)

BUSBUSY:

CLI

(Interrupt enabled)

➁ Use “Branch on Bit Set” of “BBS 5, S1, –” for the BB flag confirming and branch process.

➂ Use “STA, STX” or “STY” of the zero page addressing instruction for writing the slave address

value to the I2C data shift register (S0: address 001116).

➃ Execute the branch instruction of above ➁ and the store instruction of above ➂ continuously shown

by the above procedure example.

➄ Disable interrupts during the following three process steps:

• BB flag confirming

• Writing of slave address value

• Trigger of START condition generating

(3)

RESTART condition generating procedure in master

➀ Procedure example (The necessary conditions of the generating procedure are described as the

following ➁ to ➃). Execute the following procedure when the PIN bit is “0”.

LDM #$00, S1

(Select slave receive mode)

LDA #SLADR

(Taking out of slave address value)

SEI

(Interrupt disabled)

STA S0

(Writing of slave address value)

LDM #$F0, S1

(Trigger of RESTART condition generating)

CLI

(Interrupt enabled)

➁ Select the slave receive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. The TRX bit

becomes “0” and the SDA pin is released.

➂ The SCL pin is released by writing the slave address value to the I2C data shift register.

➃ Disable interrupts during the following two process steps:

• Writing of slave address value

(4)

Writing to I2C status register (S1: address 001316)

Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and

TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is

released and the SDA pin is released after about one machine cycle. Do not execute an instruction

to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1”. It is because it

may become the same as above.

(5)

Writing to I2C clock control register (S2: address 001516)

Do not write data into the I2C clock control register during transfer. If data is written during transfer,

the I2C clock generator is reset, so that data cannot be transferred normally.

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