M38044FFHKP datasheet(14/387 Pages) RENESAS

14 / 387 page

3804 Group (Spec.H)

List of figures

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

CHAPTER 3 APPENDIX

Fig. 3.1.1 Circuit for measuring output switching characteristics (1) ................................... 3-12

Fig. 3.1.2 Circuit for measuring output switching characteristics (2) ................................... 3-12

Fig. 3.1.3 Timing diagram (in single-chip mode) ..................................................................... 3-13

Fig. 3.1.4 Timing diagram of multi-master I2C-BUS ................................................................ 3-14

Fig. 3.2.1 Power source current standard characteristics (in high-speed mode) ............... 3-15

Fig. 3.2.2 Power source current standard characteristics (in middle-speed mode) ........... 3-15

Fig. 3.2.3 Power source current standard characteristics (in low-speed mode) ................. 3-16

Fig. 3.2.4 Power source current standard characteristics (in high-speed mode, f(XIN) = 16.8

MHz, WAIT state) ....................................................................................................... 3-16

Fig. 3.2.5 Power source current standard characteristics (in middle-speed mode, f(XIN) = 16.8

MHz, WAIT state) ....................................................................................................... 3-17

Fig. 3.2.6 Power source current standard characteristics (in low-speed mode, WAIT state) ...... 3-17

Fig. 3.2.7 Power source current standard characteristics (in high-speed mode, f(XIN) = 16.8

MHz, A/D converter operating) ................................................................................. 3-18

Fig. 3.2.8 Power source current standard characteristics (at oscillation stopping) ............ 3-18

Fig. 3.2.9 CMOS output port P-channel side characteristics (Ta = 25 °C) ......................... 3-19

Fig. 3.2.10 CMOS output port N-channel side characteristics (Ta = 25 °C) ...................... 3-19

Fig. 3.2.11 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C) .... 3-20

Fig. 3.2.12 CMOS large current output port N-channel side characteristics (Ta = 25 °C) .... 3-20

Fig. 3.2.13 CMOS input port at pull-up characteristics (Ta = 25 °C) .................................. 3-21

Fig. 2.8.7 Relevant registers setting ....................................................................................... 2-136

Fig. 2.8.8 Control procedure ..................................................................................................... 2-137

Fig. 2.9.1 Memory map of registers relevant to watchdog timer ........................................ 2-139

Fig. 2.9.2 Structure of Watchdog timer control register ....................................................... 2-139

Fig. 2.9.3 Structure of CPU mode register ............................................................................ 2-140

Fig. 2.9.4 Watchdog timer connection and division ratio setting ........................................ 2-141

Fig. 2.9.5 Relevant registers setting ....................................................................................... 2-142

Fig. 2.9.6 Control procedure ..................................................................................................... 2-142

Fig. 2.10.1 Example of poweron reset circuit ........................................................................ 2-143

Fig. 2.10.2 RAM backup system .............................................................................................. 2-143

Fig. 2.11.1 Structure of CPU mode register .......................................................................... 2-145

Fig. 2.11.2 Connection diagram ............................................................................................... 2-146

Fig. 2.11.3 Status transition diagram during power failure .................................................. 2-146

Fig. 2.11.4 Setting of relevant registers ................................................................................. 2-147

Fig. 2.11.5 Control procedure ................................................................................................... 2-148

Fig. 2.12.1 Oscillation stabilizing time at restoration by reset input .................................. 2-150

Fig. 2.12.2 Execution sequence example at restoration by occurrence of INT0 interrupt request ... 2-152

Fig. 2.12.3 Reset input time ..................................................................................................... 2-154

Fig. 2.13.1 Memory map of M38049FFHSP/FP/HP/KP ........................................................ 2-156

Fig. 2.13.2 Memory map of registers relevant to flash memory ......................................... 2-157

Fig. 2.13.3 Structure of Flash memory control register 0 .................................................... 2-157

Fig. 2.13.4 Structure of Flash memory control register 1 .................................................... 2-158

Fig. 2.13.5 Structure of Flash memory control register 2 .................................................... 2-158

Fig. 2.13.6 Rewrite example of built-in flash memory in standard serial I/O mode ......... 2-162

Fig. 2.13.7 Connection example in standard serial I/O mode (1) ....................................... 2-163

Fig. 2.13.8 Connection example in standard serial I/O mode (2) ....................................... 2-163

Fig. 2.13.9 Connection example in standard serial I/O mode (3) ....................................... 2-164

Fig. 2.13.10 Example of rewrite system for built-in flash memory in CPU rewrite mode (single-

chip mode) ............................................................................................................ 2-165

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