M38044FFHKP datasheet(324/387 Pages) RENESAS

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3-34

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.3 Notes on use

(7)

Transmit interrupt request when transmit enable bit is set

When using the transmit interrupt, take the following sequence.

➀ Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “0” (disabled).

➁ Set the tranasmit enable bit to “1”.

➂ Set the serial I/Oi transmit interrupt request bit (i = 1, 3) to “0” after 1 or more instruction has

executed.

➃ Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “1” (enabled).

q Reason

When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift

Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt

request is generated and the transmit interrupt request bit is set at this point.

(8)

Writing to baud rate generator i (BRGi) (i = 1, 3)

Write data to the baud rate generator i (BRGi) (i = 1, 3) while the transmission/reception operation

is stopped.

3.3.7 Notes on multi-master I2C-BUS interface

(1)

Read-modify-write instruction

Each register of the multi-master I2C-BUS interface has bits to change by hardware. The precautions

when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the

multi-master I2C-BUS interface are described below.

➀ I2C data shift register (S0: address 001116)

When executing the read-modify-write instruction for this register during transfer, data may become

a value not intended.

➁ I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF716 to 0FF916)

When the read-modify-write instruction is executed for this register at detecting the STOP condition,

data may become a value not intended.

q Reason

________

It is because hardware changes the read/write bit (RWB) at detecting the STOP condition.

➂ I2C status register (S1: address 001316)

Do not execute the read-modify-write instruction for this register because all bits of this register

are changed by hardware.

➃ I2C control register (S1D: address 001416)

When the read-modify-write instruction is executed for this register at detecting the START condition

or at completing the byte transfer, data may become a value not intended.

q Reason

Because hardware changes the bit counter (BC0 to BC2).

➄ I2C clock control register (S2: address 001516)

The read-modify-write instruction can be executed for this register.

➅ I2C START/STOP condition control register (S2D: address 001616)

The read-modify-write instruction can be executed for this register.

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