M38041FFHKP datasheet(328/387 Pages) RENESAS

328 / 387 page

3-38

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.3 Notes on use

(2)

Switch between middle/high-speed mode and low-speed mode

If you switch the mode between middle/high-speed and low-speed, stabilize both XIN and XCIN oscillations.

The sufficient time is required for the sub clock to stabilize, especially immediately after power on

and at returning from stop mode. When switching the mode between middle/high-speed and low-

speed, set the frequency on condition that f(XIN) > 3f(XCIN).

3.3.11 Notes on D/A converter

(1)

Vcc when using D/A converter

The D/A converter accuracy when Vcc is 4.0 V or less differs from that of when Vcc is 4.0 V or more.

When using the D/A converter, we recommend using a Vcc of 4.0 V or more.

(2)

DAi conversion register when not using D/A converter

When a D/A converter is not used, set all values of the DAi conversion registers (i = 1, 2) to “0016”.

The initial value after reset is “0016”.

3.3.12 Notes on watchdog timer

qMake sure that the watchdog timer H does not underflow while waiting Stop release, because the

watchdog timer keeps counting during that term.

qWhen the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program.

3.3.13 Notes on RESET pin

Connecting capacitor

In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the

RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When

connecting the capacitor, note the following :

• Make the length of the wiring which is connected to a capacitor as short as possible.

• Be sure to verify the operation of application products on the user side.

q Reason

____________

If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may

cause a microcomputer failure.

3.3.14 Notes on low-speed operation mode

(1)

Using sub-clock

To use a sub-clock, fix bit 3 of the CPU mode

3.3.4) resistance value to a certain level to

stabilize an oscillation. For resistance value

of Rd, consult the oscillator manufacturer.

q Reason

When bit 3 of the CPU mode register is set

to “0”, the sub-clock oscillation may stop.

CCIN

CCOUT

XCIN

XCOUT

Fig. 3.3.4 Ceramic resonator circuit

M38041FFHKP датащи(PDF) 328 Page - Renesas Technology Corp

M38041FFHKP датащи(HTML) 328 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL