M38041FFHKP datasheet(332/387 Pages) RENESAS

332 / 387 page

3-42

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.3 Notes on use

(4)

JMP instruction

When using the JMP instruction in indirect addressing mode, do not specify the last address on a

page as an indirect address.

(5)

Multiplication and Division Instructions

• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.

• The execution of these instructions does not change the contents of the processor status register.

(6)

Ports

The contents of the port direction registers cannot be read. The following cannot be used:

• The data transfer instruction (LDA, etc.)

• The operation instruction when the index X mode flag (T) is “1”

• The instruction with the addressing mode which uses the value of a direction register as an index

• The bit-test instruction (BBC or BBS, etc.) to a direction register

• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register.

Use instructions such as LDM and STA, etc., to set the port direction registers.

3.3.21 Notes on flash memory version

The CNVss pin determines the flash memory mode. To improve the noise reduction, connect a track

between CNVss pin and Vss pin or Vcc pin with 1 to 10km resistance. The mask ROM version track of

CNVss pin has no operational interference even if it is connected to Vss pin or Vcc pin via a resistor.

3.3.22 Notes on electric characteristic differences between mask ROM and flash nemory version MCUs

There are differences in electric characteristics, operation margin, noise immunity, and noise radiation

between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes,

built-in ROM, and layout pattern etc. When manufacturing an application system with the Flash Memory

version and then switching to use of the Mask ROM version, please conduct evaluations equivalent to the

system evaluations conducted for the flash memory version.

3.3.23 Notes on handling of power source pins

In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass

capacitor between power source pin (Vcc pin) and GND pin (Vss pin), and between power source pin (Vcc

pin) and analog power source input pin (AVss pin). Besides, connect the capacitor to as close as possible.

For bypass capacitor which should not be located too far from the pins to be connected, a ceramic

capacitor of 0.01

µF–0.1 µF is recommended.

3.3.24 Power Source Voltage

When the power source voltage value of a microcomputer is less than the value which is indicated as the

recommended operating conditions, the microcomputer does not operate normally and may perform unstable

operation.

In a system where the power source voltage drops slowly when the power source voltage drops or the

power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended

operating conditions and design a system not to cause errors to the system by this unstable operation.

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