M38041FFHKP datasheet(326/387 Pages) RENESAS

326 / 387 page

3-36

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.3 Notes on use

3.3.8 Notes on programming for SMBUS interface

(1)

Time out process

For a smart battery system, the time out process with a program is required so that the communication

can be completed even when communication is interrupted. It is because there is possibility of

extracting a battery from a PC.

The specifications are defined so that communication has been able to be completed within 25 ms

from START condition to STOP condition and within 10 ms from the ACK pulse to the ACK pulse of

each byte. Accordingly, the following two should be considered as count start conditions.

➀ SDA falling edge caused by SCL/SDA interrupt

This is the countermeasure for a communication interrupt in the middle of from START condition

to a slave address. However, the detection condition must be considered because a interrupt is

also generated by communication from other masters to other slaves.

➁ SMBUS interrupt after receiving slave address

This is the countermeasure for when communication is interrupted from receiving a slave address

until receiving a command.

(2)

Low hold of communication line

The I2C-BUS interface conforms to the I2C-BUS Standard Specifications. However, because the use

condition of SMBUS differs from the I2C-BUS’s, there is possibility of occurrence of the following

problem.

➀ Low hold of SDA line caused by ACK pulse at voltage drop of communication line

When the SMBUS voltage slowly drops, that is caused by extracting a battery from equipment or

turning off a PC’s power or etc., it might be incorrectly treated as the SCL pulse near the threshold

level voltage.

When the SDA is judged “L” in that condition, it becomes the general call and the ACK is transmitted.

However, when the SCL remains “L” at the ACK pulse, the SDA continuously remains “L” until

input of the next SCL pulse.

(6)

Switching of SCL/SDA interrupt pin polarity selection bit, SCL/SDA interrupt pin selection bit,

I2C-BUS interface enable bit

When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt

pin selection bit, or the I2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be

set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt

pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bit

ES0 is set. Reset the request bit to “0” after setting these bits, and enable the interrupt.

(7)

Process of after STOP condition generating in master mode

Do not write data in the I2C data shift register (S0) and the I2C status register (S1) until the bus busy

flag BB becomes “0” after generating the STOP condition in the master mode. It is because the

STOP condition waveform might not be normally generated. Reading to the above registers does not

have the problem.

(8)

ES0 bit switch

In standard clock mode when SSC = “000102” or in high-speed clock mode, flag BB may switch to

“1” if ES0 bit is set to “1” when SDA is “L”.

Countermeasure:

Set ES0 to “1” when SDA is “H”.

• Trigger of RESTART condition generating

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