M38041FFHKP datasheet(322/387 Pages) RENESAS

322 / 387 page

3-32

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.3 Notes on use

3.3.6 Notes on serial interface

(1)

Notes when selecting clock synchronous serial I/O

➀ Stop of transmission operation

As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous

(UART) serial I/O, clear the serial I/Oi enable bit and the transmit enable bit to “0” (serial I/Oi and

transmit disabled).

q Reason

Since transmission is not stopped and the transmission circuit is not initialized even if only the

serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled), the internal transmission is running (in

this case, since pins TxDi, RxDi, SCLKi, and SRDYi function as I/O ports, the transmission data is

not output). When data is written to the transmit buffer register in this state, data starts to be

shifted to the transmit shift register. When the serial I/Oi enable bit is set to “1” at this time, the

data during internally shifting is output to the TxDi pin and an operation failure occurs.

➁ Stop of receive operation

As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous

(UART) serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/Oi

enable bit to “0” (serial I/Oi disabled).

➂ Stop of transmit/receive operation

As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous

(UART) serial I/O, clear both the transmit enable bit and receive enable bit to “0” (transmit and

receive disabled).

(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data

transmission and reception cannot be stopped.)

q Reason

In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.

If any one of transmission and reception is disabled, a bit error occurs because transmission and

reception cannot be synchronized.

In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,

the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit

disabled). Also, the transmission circuit is not initialized by clearing the serial I/Oi enable bit to “0”

(serial I/Oi disabled) (refer to ➀ in (1) ).

M38041FFHKP датащи(PDF) 322 Page - Renesas Technology Corp