M38041FFHKP datasheet(360/387 Pages) RENESAS

360 / 387 page

3-70

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.5 Control registers

Fig. 3.5.31 Structure of UART3 control register

UART3 control register

b7 b6 b5 b4 b3 b2 b1 b0

UART3 control register

(UART3CON: address 003316)

0: 8 bits

1: 7 bits

Character length

selection bit (CHAS)

Parity enable bit

(PARE)

Stop bit length

selection bit (STPS)

P35/TxD3 P-channel

output disable bit

(POFF)

Parity selection bit

(PARS)

Functions

Name

At reset R W

Nothing is arranged for these bits. These are

write disabled bits. When these bits are read

out, the contents are “1”.

0: Parity checking disabled

1: Parity checking enabled

0: Even parity

1: Odd parity

0: 1 stop bit

1: 2 stop bits

0: CMOS output

(in output mode)

1: N-channel open-drain

output (in output mode)

Fig. 3.5.32 Structure of AD/DA control register

AD/DA control register

b7 b6 b5 b4 b3 b2 b1 b0

AD/DA control register

(ADCON: address 003416)

Name

Functions

At reset R W

Analog input pin

selection bits 1

b2 b1 b0

0 0 0: P60/AN0 or P00/AN8

0 0 1: P61/AN1 or P01/AN9

0 1 0: P62/AN2 or P02/AN10

0 1 1: P63/AN3 or P03/AN11

1 0 0: P64/AN4 or P04/AN12

1 0 1: P65/AN5 or P05/AN13

1 1 0: P66/AN6 or P06/AN14

1 1 1: P67/AN7 or P07/AN15

Analog input pin

selection bit 2

0: AN0 to AN7 side

1: AN8 to AN15 side

AD conversion

completion bit

0: Conversion in progress

1: Conversion completed

DA1 output enable

bit

0: DA1 output disabled

1: DA1 output enabled

DA2 output enable

bit

0: DA2 output disabled

1: DA2 output enabled

5 Nothing is arranged for this bit. This is a write

disabled bit. When this bit is read out, the

contents are “0”.

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