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TMS320DM335 датащи(PDF) 1 Page - Texas Instruments

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номер детали TMS320DM335
подробное описание детали  Digital Media System-on-Chip (DMSoC)
PDF  158 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM335 датащи(HTML) 1 Page - Texas Instruments

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TMS320DM335 Digital Media System-on-Chip (DMSoC)
1.1 Features
TMS320DM335
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS528A – JULY 2008 – REVISED AUGUST 2008
encoder
• High-Performance Digital Media
System-on-Chip
• External Memory Interfaces (EMIFs)
135-, 216-, and 270-MHz ARM926EJ-S™
DDR2 and mDDR SDRAM 16-bit wide EMIF
Clock Rate
With 256 MByte Address Space (1.8-V I/O)
Fully Software-Compatible With ARM9
Asynchronous16-/8-bit Wide EMIF (AEMIF)
Extended Temperature 216-MHz Devices
• Flash Memory Interfaces
are Available
NAND (8-/16-bit Wide Data)
• ARM926EJ-S Core
OneNAND(16-bit Wide Data)
Support for 32-Bit and 16-Bit (Thumb Mode)
• Flash Card Interfaces
Instruction Sets
Two Multimedia Card (MMC) / Secure
DSP Instruction Extensions and Single
Digital (SD/SDIO)
Cycle MAC
SmartMedia
ARM® Jazelle® Technology
• Enhanced Direct-Memory-Access (EDMA)
EmbeddedICE-RT™ Logic for Real-Time
Controller (64 Independent Channels)
Debug
• USB Port with Integrated 2.0 High-Speed PHY
• ARM9 Memory Architecture
that Supports
16K-Byte Instruction Cache
USB 2.0 Full and High-Speed Device
8K-Byte Data Cache
USB 2.0 Low, Full, and High-Speed Host
32K-Byte RAM
• Three 64-Bit General-Purpose Timers (each
8K-Byte ROM
configurable as two 32-bit timers)
Little Endian
• One 64-Bit Watch Dog Timer
• Video Processing Subsystem
• Three UARTs (One fast UART with RTS and
Front End Provides:
CTS Flow Control)
• Hardware IPIPE for Real-Time Image
• Three Serial Port Interfaces (SPI) each with
Processing
two Chip-Selects
• Up to 14-bit CCD/CMOS Digital Interface
• One Master/Slave Inter-Integrated Circuit (I2C)
Bus®
• 16-/8-bit Generic YcBcR-4:2 Interface
(BT.601)
• Two Audio Serial Port (ASP)
• 10-/8-bit CCIR6565/BT655 Interface
I2S and TDM I2S
• Up to 75-MHz Pixel Clock
AC97 Audio Codec Interface
• Histogram Module
S/PDIF via Software
• Resize Engine
Standard Voice Codec Interface (AIC12)
Resize Images From 1/16x to 8x
SPI Protocol (Master Mode Only)
Separate Horizontal/Vertical Control
• Four Pulse Width Modulator (PWM) Outputs
Two Simultaneous Output Paths
• Four RTO (Real Time Out) Outputs
Back End Provides:
• Up to 104 General-Purpose I/O (GPIO) Pins
• Hardware On-Screen Display (OSD)
(Multiplexed with Other Device Functions)
• Composite NTSC/PAL video encoder
• On-Chip ARM ROM Bootloader (RBL) to Boot
output
From NAND Flash, MMC/SD, or UART
• 8-/16-bit YCC and Up to 18-Bit RGB666
• Configurable Power-Saving Modes
Digital Output
• Crystal or External Clock Input (typically
• BT.601/BT.656 Digital YCbCr 4:2:2
24 MHz or 36 MHz)
(8-/16-Bit) Interface
• Flexible PLL Clock Generators
• Supports digital HDTV (720p/1080i)
• Debug Interface Support
output for connection to external
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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