L-Channel

R-Channel

LRCK

SCLK

DATA

N−1 N−2

N−3

N−1

N−2

MSB

0

LSB

1

2

0

MSB

N–2

N–1

LSB

1

2

N–3

Left-Justified

L-Channel

R-Channel

LRCK

SLCK

DATA

N−1

N−2

N−3

0

N−1

N−2

N−3

0

1

2

MSB

LSB

LSB

MSB

1

2

N–1

N–2

Right-Justified

TAS5701

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it

is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,

toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused

trailing data bit positions.

Figure 19. Left-Justified Format

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when

it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at

24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before

LRCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks

unused leading data bit positions.

18

Submit Documentation Feedback

Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TAS5701